xilinx PL测 DP 点屏 /接收（三）--TX

环境：

a)硬件：官方ZCU106开发板 , tb-fmch-vfmc-dp子卡。

b)软件：vivado2021.1，vitis2021.1，裸机程序。

1、例程：

 

 

1、DP TX ip速率：

 

2、框架：

 

3、重要寄存器：

 

 

 

 

 

4、

 

5、时钟

 

6、像素排列：

AXI4_STREAM:

 NATIVE:

 

vitis代码分析：

 

DP TX的初始化：

u32 Dptx_init(void)

{

u32 Status;

XDpTxSs_Config *ConfigPtr_tx;   

xil_printf("config dp tx \n\r");

ConfigPtr_tx = XDpTxSs_LookupConfig(XDPTXSS_DEVICE_ID);

if (!ConfigPtr_tx) {

xil_printf("DPTXSS Lookup Config failed.\r\n");

return XST_FAILURE;

}

xil_printf("DPTXSS Lookup Config done.\r\n");

Status = XDpTxSs_CfgInitialize(&DpTxSsInst, ConfigPtr_tx,ConfigPtr_tx->BaseAddress);

if (Status != XST_SUCCESS) {

xil_printf("DPTXSS config initialization failed.\r\n");

return XST_FAILURE;

}

xil_printf("DPTXSS config initialization done.\r\n");

/* Check for SST/MST support */

if (DpTxSsInst.UsrOpt.MstSupport) {

xil_printf("INFO:DPTXSS is MST enabled. DPTXSS can be "

"switched to SST/MST\r\n");

} else {

xil_printf("INFO:DPTXSS is SST enabled. DPTXSS works "

"only in SST mode.\r\n");

}

return XST_SUCCESS;

}

 

DP TX的中断申请：

u32 DpTxSs_SetupIntrSystem(void)

{

//    u32 Status = XST_SUCCESS;

//    XINTC *IntcInstPtr = &IntcInst;

/* Set custom timer wait */

//    XDpTxSs_SetUserTimerHandler(&DpTxSsInst, &DpPt_CustomWaitUs, &TmrCtr);

XDpTxSs_SetCallBack(&DpTxSsInst, (XDPTXSS_HANDLER_DP_HPD_EVENT),        &DpPt_HpdEventHandler, &DpTxSsInst);

XDpTxSs_SetCallBack(&DpTxSsInst, (XDPTXSS_HANDLER_DP_HPD_PULSE),        &DpPt_HpdPulseHandler, &DpTxSsInst);

XDpTxSs_SetCallBack(&DpTxSsInst, (XDPTXSS_HANDLER_DP_LINK_RATE_CHG),    &DpPt_LinkrateChgHandler, &DpTxSsInst);

// XDpTxSs_SetCallBack(&DpTxSsInst, (XDPTXSS_HANDLER_DP_PE_VS_ADJUST),        &DpPt_pe_vs_adjustHandler, &DpTxSsInst);

// XDpTxSs_SetCallBack(&DpTxSsInst, (XDPTXSS_HANDLER_DP_EXT_PKT_EVENT),    &DpTxSs_ExtPacketHandler, &DpTxSsInst);

// XDpTxSs_SetCallBack(&DpTxSsInst, (XDPTXSS_HANDLER_DP_VSYNC),            &DpTxSs_VsyncHandler, &DpTxSsInst);

return (XST_SUCCESS);

}

 

 

DP TX的发送视频参数获取：

中断，PHY，请看RX的文章

void dp_tx_format()

{

user_config.user_bpc = 8;

//  XVIDC_VM_1920x1080_60_P_RB

user_config.VideoMode_local =XVIDC_VM_3840x2160_30_P ; //  XVIDC_VM_1920x1080_60_P

user_config.user_pattern = 1; /*Color Ramp (Default)*/

user_config.user_format = XVIDC_CSF_RGB;

PixelWidth =4;

u32 freq;

u32 h_total,v_total,frame;

h_total = XVidC_VideoTimingModes[user_config.VideoMode_local].Timing.HTotal;

v_total = XVidC_VideoTimingModes[user_config.VideoMode_local].Timing.F0PVTotal;

frame = XVidC_VideoTimingModes[user_config.VideoMode_local].FrameRate;

freq = h_total * v_total * frame/PixelWidth/1000;

xil_printf(" VideoMode_local = %d \r\n",user_config.VideoMode_local);

xil_printf("h_total = %d , v_total = %d ,frame =%d ,freq = %d ---------------------\r\n",h_total,v_total,frame,freq);

ComputeMandD(freq,CLK_TX_BASE);

}

 

DP TX 开始training：

u32 DpTx_Setup(void)

{

u8 LineRate_init = DP_LINK_RATE;

u8 LaneCount_init = DP_LANE_COUNT;

u8 Edid_org[128], Edid1_org[128];

u8 connected = 0;

DpTxSs_Setup(&LineRate_init, &LaneCount_init, Edid_org, Edid1_org);   //  获取 rx的信息，比如最大lane数目，最大速率等，和edid，如果知道rx的信息，这里可以不用读取edid的

xil_printf("DpTxSs_Setup done.\r\n");

while (!XDpTxSs_IsConnected(&DpTxSsInst)) {

if (connected == 0) {

xil_printf(    "Please connect a DP Monitor to start the application !!!\r\n");

connected = 1;

}

    }

xil_printf(    "DP Monitor connection detected!!!\r\n");

sink_power_cycle();

//    CustomWaitUs(DpTxSsInst.DpPtr, &TmrCtr);

/* Do not return in order to allow interrupt handling to run. HPD events

 * (connect, disconnect, and pulse) will be detected and handled.

 */

DpTxSsInst.DpPtr->TxInstance.TxSetMsaCallback = NULL;

DpTxSsInst.DpPtr->TxInstance.TxMsaCallbackRef = NULL;

DpTxSsInst.DpPtr->TxInstance.MsaConfig[0].ComponentFormat = 0x0;

xil_printf("LineRate_init=%x  --- LaneCount_init=%x \r\n",LineRate_init,LaneCount_init);

xil_printf("XDP_TX_PHY_STATUS  ---%x  \r\n",XDp_ReadReg(XPAR_DPTXSS_0_BASEADDR, XDP_TX_PHY_STATUS));

xil_printf("dp tx msa: M VID0 = %d\r\n",XDp_ReadReg(XPAR_DPTXSS_0_BASEADDR, XDP_TX_M_VID));

start_tx (LineRate_init, LaneCount_init,user_config);   // 启动DP TX

xil_printf("dp tx msa: M VID2 = %d\r\n",XDp_ReadReg(XPAR_DPTXSS_0_BASEADDR, XDP_TX_M_VID));

dptx_status_report();

return XST_SUCCESS;

}

void DpTxSs_Setup(u8 *LineRate_init, u8 *LaneCount_init,u8 Edid_org[128], u8 Edid1_org[128])

{

u32 Status;

Status = XDp_ReadReg(DpTxSsInst.DpPtr->Config.BaseAddr,XDP_TX_INTERRUPT_STATUS);

xil_printf(    "DpTxSs_Setup XDP_TX_INTERRUPT_STATUS  = %X\r\n",Status);

DpTxSsInst.DpPtr->TxInstance.TxSetMsaCallback = NULL;

DpTxSsInst.DpPtr->TxInstance.TxMsaCallbackRef = NULL;

u8 connected =0 ;

// this is intentional infinite while loop

Status = XDpTxSs_IsConnected(&DpTxSsInst);

    while (!Status) {

        if (connected == 0) {

xil_printf(    "Please connect a DP Monitor to start the application !!!\r\n");

connected = 1;

}

    }

    xil_printf(    "DP Monitor connection detected!!!\r\n");

//Waking up the monitor

    sink_power_cycle();

    Status = XDpTxSs_IsConnected(&DpTxSsInst);

//reading the first block of EDID

if (Status) {

xil_printf("Reading EDID contents of the DP Monitor..\r\n");

Status  = XDp_TxAuxRead(DpTxSsInst.DpPtr,    XDP_DPCD_MAX_LINK_RATE,  1, LineRate_init);

xil_printf ("DpTxSs_Setup XDP_DPCD_MAX_LINK_RATE is %x\r\n", *LineRate_init);

Status |= XDp_TxAuxRead(DpTxSsInst.DpPtr,    XDP_DPCD_MAX_LANE_COUNT, 1, LaneCount_init);

xil_printf ("DpTxSs_Setup XDP_DPCD_MAX_LANE_COUNT is %x\r\n", *LaneCount_init);

u8 rData = 0;

// check the EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT bit

XDp_TxAuxRead(DpTxSsInst.DpPtr, XDP_DPCD_TRAIN_AUX_RD_INTERVAL, 1, &rData);

if(rData & 0x80){ // if EXTENDED_RECEIVER_CAPABILITY_FIELD is enabled

XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x2201, 1, &rData); // read maxLineRate

if(rData == XDP_DPCD_LINK_BW_SET_810GBPS){

*LineRate_init = 0x1E;

xil_printf ("Capability is %x\r\n", *LineRate_init);

}

//    xil_printf ("DpTxSs_Setup read maxLineRate is %x\r\n", rData);

}

if (Status != XST_SUCCESS) { // give another chance to monitor.

//Waking up the monitor

sink_power_cycle();

XDp_TxGetEdidBlock(DpTxSsInst.DpPtr, Edid_org, 0);

//reading the second block of EDID

XDp_TxGetEdidBlock(DpTxSsInst.DpPtr, Edid1_org, 1);

xil_printf("Reading EDID contents of the DP Monitor..\r\n");

Status = XDp_TxAuxRead(DpTxSsInst.DpPtr,    XDP_DPCD_MAX_LINK_RATE, 1, LineRate_init);

Status |= XDp_TxAuxRead(DpTxSsInst.DpPtr,    XDP_DPCD_MAX_LANE_COUNT, 1, LaneCount_init);

XDp_TxAuxRead(DpTxSsInst.DpPtr, XDP_DPCD_TRAIN_AUX_RD_INTERVAL, 1, &rData);

if(rData & 0x80){ // if EXTENDED_RECEIVER_CAPABILITY_FIELD is enabled

XDp_TxAuxRead(DpTxSsInst.DpPtr, 0x2201, 1, &rData); // read maxLineRate

if(rData == XDP_DPCD_LINK_BW_SET_810GBPS){

*LineRate_init = 0x1E;

xil_printf ("Capability is %x\r\n", *LineRate_init);

}

xil_printf ("DpTxSs_Setup read maxLineRate is %x\r\n", rData);

}

if (Status != XST_SUCCESS)

xil_printf ("Failed to read sink capabilities\r\n");

}

} else {

xil_printf("Please connect a DP Monitor and try again !!!\r\n");

return;

}

*LineRate_init &= 0xFF;

*LaneCount_init &= 0xF;

     xil_printf("System capabilities set to: LineRate %x, LaneCount %x\r\n", *LineRate_init,*LaneCount_init);

}

u32 start_tx(u8 line_rate, u8 lane_count, user_config_struct user_config)

{

XVidC_VideoMode res_table = user_config.VideoMode_local;

u8 bpc = user_config.user_bpc;

u8 format = user_config.user_format-1;

u32 Status;

XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,    XDP_TX_INTERRUPT_MASK, 0xFFF);

//Waking up the monitor

sink_power_cycle();

XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_ENABLE, 0x0);

// Give a bit of time for DP IP after monitor came up and starting Link training

usleep(100000);

XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr, XDP_TX_ENABLE, 0x1);

    xil_printf ("\r\nTraining TX with: Link rate %x, Lane count %d\r\n",line_rate,lane_count);

XDpTxSs_SetLinkRate(&DpTxSsInst, line_rate);    // 设置速率

xil_printf ("XDpTxSs_SetLinkRate end  line_rate = %x    \r\n",line_rate);

XDpTxSs_SetLaneCount(&DpTxSsInst, lane_count);   // 设置lane的数目

xil_printf ("XDpTxSs_SetLaneCount end lane_count = %x   \r\n",lane_count);

if (res_table !=0) {

Status = XDpTxSs_SetVidMode(&DpTxSsInst, res_table);

if (Status != XST_SUCCESS) {

xil_printf("ERR: Setting resolution failed\r\n");

}

}

if (bpc !=0 ) {

Status = XDpTxSs_SetBpc(&DpTxSsInst, bpc);

if (Status != XST_SUCCESS){

xil_printf("ERR: Setting bpc to %d failed\r\n",bpc);

}

}

XDpTxSs_SetUserPixelWidth(&DpTxSsInst,4,XDP_TX_STREAM_ID1);  // 设置每个时钟的pixel

DpTxSsInst.DpPtr->TxInstance.MsaConfig[XDP_TX_STREAM_ID1-1].OverrideUserPixelWidth =PixelWidth;

XDp_TxCfgSetColorEncode(DpTxSsInst.DpPtr, XDP_TX_STREAM_ID1, format, XVIDC_BT_601, XDP_DR_CEA);

Status = DpTxSubsystem_Start(&DpTxSsInst);

if (Status != XST_SUCCESS) {

xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR: ""DP SS Start setup failed!\n\r");

}

xil_printf (".\r\n");

xil_printf (".\r\n");

xil_printf (".\r\n");

Status = XDpTxSs_CheckLinkStatus(&DpTxSsInst);   // 检测是否training成功

if (Status != (XST_SUCCESS)) {

xil_printf ("*");

XDpTxSs_SetLinkRate(&DpTxSsInst, line_rate);

XDpTxSs_SetLaneCount(&DpTxSsInst, lane_count);

Status = DpTxSubsystem_Start(&DpTxSsInst);

if (Status != XST_SUCCESS) {

xil_printf("ERR:DPTX SS start failed\r\n");

return (XST_FAILURE);

}

}

/* Mask unsused interrupts

 *

 */

XDp_WriteReg(DpTxSsInst.DpPtr->Config.BaseAddr,    XDP_TX_INTERRUPT_MASK, 0x0);

xil_printf ("..done !\r\n");

//    tx_started = 1;

return XST_SUCCESS;

}