FPGA学习笔记（五）——状态机设计

第一段：同步时序的always模块，格式化描述次态迁移到现态寄存器。

always@(posedge clk or negedge rst_t) begin
if(!rst_n) begin
   state_c <= IDLE;
end
else begin
   state_c <= state_n;
end
end

第二段：组合逻辑的always模块，描述状态转移条件。
 

always@(*) begin
case(state_c)
 IDLE:begin
  if(idle2s1_start) begin
   state_n = S1;
  end
  else begin
   state_n = state_c;
  end
 end
 S1: begin
  if(s12s2_start) begin
   state_n = S2;
  end
  else begin
   state_n = state_c;
 end
 end
 S2: begin
  if(s22idle_start) begin
   state_n = IDLE;
  end
  else begin
   state_n = state_c;
  end
  end
 default: begin
  state_n = IDLE;
 end
 endcase
end

第三段：定义状态转移条件。

assign idle2s1_start = state_c==IDLE &&;
assign s12s2_start = state_c==S1 &&;
assign s22idle_start = state_c==S2 &&;

第四段：设计输出。

always@(posedge clk or negedge rst_t)
 if(!rst_n) begin
  out1<=1'b0;
 end
 else if(state_c==S1) begin
  out1<=1'b1;
 end
 else begin
  out1<=1'b0;
 end
 end