Systemverilog | Test Bench Environment | Half Adder

https://www.youtube.com/watch?v=9ygbJ_rjZHU
Systemverilog | Test Bench Environment | Half Adder

https://www.youtube.com/watch?v=1oFlRtw_g18

module half_adder(s,c,a,b);
input a,b;
output s,c;

xor x1(s,a,b);
and a1(c,a,b);
endmodule


class transaction;

rand bit a;
rand bit b;

bit sum;
bit carry;

function void display(string name);
	$display("----------------");
	$display("---%s---------",name);
	$display("----------------");
	$display("a=%0d, c=%0d",a,b);
	$display("sum=%0d, carry=%0d",sum,carry);
	$display("----------------");
	
endfunction

endclass


`include "intf.sv"
`include "test.sv"

module tbench_top;

	intf i_intf();
	test t1(i_intf);
	
	half_adder h1(
		.a(i_intf.a),
		.b(i_intf.b),
		.s(i_intf.sum),
		.c(i_intf.carry)
	);
	
	initial begin
		$dumpfile("dump.vcd");
		$dumpvars;
	end
endmodule


class generator;
	
	transaction trans;
	mailbox gen2driv;
	
	function new(mailbox gen2driv);
		this.gen2driv = gen2driv;
	endfunction
	
	task main();
		repeat(1)
			begin
				trans=new();
				trans.randomize();
				trans.display("generator");
				gen2driv.put(trans);
			end
	endtask
endclass

class driver;
	virtual intf vif;
	
	mailbox gen2driv;
	
	function new(virtual intf vif,mailbox gen2driv);
		this.vif = vif;
		this.gen2driv = gen2driv;
	endfunction
	
	task main;
		repeat(1)
			begin
				transaction trans;
				gen2driv.get(trans);
				vif.a = trans.a;
				vif.b = trans.b;
				trans.sum = vif.sum;
				trans.carry = vif.carry;
				trans.display("driver");
			end
	endtask
endclass


interface intf();
	logic a;
	logic b;
	logic sum;
	logic carry;
endinterface


class monitor;
	virtual intf vif;
	
	mailbox mon2scb;
	
	function new(virtual intf vif,mailbox mon2scb);
		this.vif = vif;
		this.mon2scb = mon2scb;
	endfunction
	
	task main;
		repeat(1)
			#3
			begin
				transaction trans;
				trans  =new();
				
				trans.a = vif.a  ;
				trans.b = vif.b ;
				vif.sum = trans.sum ;
				vif.carry = trans.carry;
				mon2scb.put(trans);
				trans.display("monitor");
			end
	endtask
endclass


class scoreboard;
	
	mailbox mon2scb;
	function new(mailbox mon2scb );
		this.mon2scb = mon2scb;
	endfunction
	
	task main;
		transaction trans;
		repeat(1)
			begin
				mon2scb.get(trans);
				if(((trans.a ^ trans.b)==trans.sum) && ((trans.a & trans.b)==trans.carry))
					$display("rst is ok");
				else
					$error("error rst");
				
				trans.display("monitor");
			end
	endtask
endclass


`include "transaction.sv"
`include "generator.sv"
`include "driver.sv"
`include "monitor.sv"
`include "scoreboard.sv"

class enviroment;
	generator gen;
	driver driv;
	monitor mon;
	scoreboard scb;
	mailbox m1;
	mailbox m2;
	
	virtual intf vif;
	function new(virtual intf vif);
		this.vif  = vif;
		m1= new();
		m2= new();
		gen = new(m1);
		driv = new(vif,m1);
		mon=new(vif,m2);
		scb = new(m2);
	endfunction
	
	task test();
		fork
			gen.main();
			driv.main();
			mon.main();
			scb.main();
		join
	endtask
	
	task run;
		test();
		$finish;
	endtask
	
endclass

`include "enviroment.sv"
program test(intf i_intf);
	
	enviroment env;
	initial begin
		env = new(i_intf);
		env.run();
	end
endprogram

[2024-01-22 06:52:56 UTC] qrun -autoorder -batch -access=rw+/.  -vcom.options '-timescale' '1ns/1ns'  -end -mfcu design.sv testbench.sv  -vsim.options '-voptargs=+acc=npr'  -end  -do  " run -all; exit"  
QuestaSim-64 qrun 2021.3 Utility 2021.07 Jul 13 2021
Start time: 01:52:57 on Jan 22,2024
qrun -autoorder -batch -access=rw+/. -vcom.options -timescale 1ns/1ns -end -mfcu design.sv testbench.sv -vsim.options -voptargs="+acc=npr" -end -do " run -all; exit" 
Creating library 'qrun.out/work'.
QuestaSim-64 vlog 2021.3 Compiler 2021.07 Jul 13 2021
Start time: 01:52:57 on Jan 22,2024
vlog -mfcu design.sv testbench.sv -work qrun.out/work -csession=incr -writesessionid "+qrun.out/top_dus" -statslog qrun.out/stats_log 
-- Compiling module half_adder
-- Compiling interface intf
-- Compiling package design_sv_unit
** Warning: generator.sv(14): (vlog-2240) Treating stand-alone use of function 'randomize' as an implicit VOID cast.
-- Compiling program test
-- Compiling module tbench_top

Top level modules:
	tbench_top
End time: 01:52:57 on Jan 22,2024, Elapsed time: 0:00:00
Errors: 0, Warnings: 1
QuestaSim-64 vopt 2021.3 Compiler 2021.07 Jul 13 2021
Start time: 01:52:57 on Jan 22,2024
vopt -access=rw+/. -mfcu -findtoplevels /home/runner/qrun.out/work+0+ -work qrun.out/work -statslog qrun.out/stats_log -o qrun_opt 

Top level modules:
	tbench_top

Analyzing design...
-- Loading module tbench_top
-- Loading interface intf
-- Loading program test
-- Loading module half_adder
Optimizing 6 design-units (inlining 2/4 module instances):
-- Optimizing package design_sv_unit(fast)
** Warning: generator.sv(14): (vopt-2240) Treating stand-alone use of function 'randomize' as an implicit VOID cast.
-- Inlining interface intf(fast__2)
-- Inlining module half_adder(fast)
-- Optimizing module tbench_top(fast)
-- Optimizing program test(fast)
-- Optimizing interface intf(fast)
Optimized design name is qrun_opt
End time: 01:52:58 on Jan 22,2024, Elapsed time: 0:00:01
Errors: 0, Warnings: 1
# vsim -batch -voptargs="+acc=npr" -lib qrun.out/work -do " run -all; exit" -statslog qrun.out/stats_log qrun_opt -appendlog -l qrun.log 
# Start time: 01:52:58 on Jan 22,2024
# //  Questa Sim-64
# //  Version 2021.3 linux_x86_64 Jul 13 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading sv_std.std
# Loading work.design_sv_unit(fast)
# Loading work.tbench_top(fast)
# Loading work.test(fast)
# Loading work.intf(fast)
# 
# run -all
# ----------------
# ---generator---------
# ----------------
# a=1, c=0
# sum=0, carry=0
# ----------------
# ----------------
# ---driver---------
# ----------------
# a=1, c=0
# sum=0, carry=0
# ----------------
# ----------------
# ---monitor---------
# ----------------
# a=1, c=0
# sum=0, carry=0
# ----------------
# ** Error: error rst
#    Time: 3 ns  Scope: design_sv_unit.scoreboard.main File: scoreboard.sv Line: 17
# ----------------
# ---monitor---------
# ----------------
# a=1, c=0
# sum=0, carry=0
# ----------------
# ** Note: $finish    : enviroment.sv(37)
#    Time: 3 ns  Iteration: 0  Instance: /tbench_top/t1
# End time: 01:52:59 on Jan 22,2024, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0
# *** Summary *********************************************
#     qrun: Errors:   0, Warnings:   0
#     vlog: Errors:   0, Warnings:   1
#     vopt: Errors:   0, Warnings:   2
#     vsim: Errors:   1, Warnings:   0
#   Totals: Errors:   1, Warnings:   3
Finding VCD file...
./dump.vcd
[2024-01-22 06:52:59 UTC] Opening EPWave...
Done

#makefile    -mfcu 就可以去掉文件之间的include
FILE ?= tbench_top
all : work comp sim


work: 
	vlib work
comp:
	#vlog half_adder.sv  transaction.sv generator.sv driver.sv intf.sv monitor.sv scoreboard.sv enviroment.sv test.sv $(FILE).sv
	#vlog half_adder_pkg.sv half_adder.sv test.sv $(FILE).sv  
	vlog -mfcu -sv -f filelist.f half_adder.sv  $(FILE).sv  

sim:
	vsim -c -do 'run -all; exit' $(FILE) -l $(FILE).log -voptargs=+acc