chisel fifo

// Hello World
import chisel3._
/*
class Hello extends Module {
  val io = IO(new Bundle {
    val led = Output(UInt(1.W))
  })
  val CNT_MAX = (50000000 / 2 - 1).U

  val cntReg = RegInit(0.U(32.W))
  val blkReg = RegInit(0.U(1.W))

  cntReg := cntReg + 1.U
  when(cntReg === CNT_MAX) {
    cntReg := 0.U
    blkReg := ~blkReg
  }
  io.led := blkReg
}
 */

import chisel3.util._
class FifoController(width: Int, depth: Int) extends Module {
  val io = IO(new Bundle {
    val enq = Flipped(Decoupled(UInt(width.W)))
    val deq = Decoupled(UInt(width.W))
    val count = Output(UInt(log2Ceil(depth + 1).W))
  })
  // 定义FIFO的存储器
  val mem = SyncReadMem(depth, UInt(width.W))
  // 定义FIFO的读写指针
  val pointer = RegInit(0.U(log2Ceil(depth).W))
  val enqPtr = pointer
  val deqPtr = pointer
  // 定义FIFO的计数器
  val count = RegInit(0.U(log2Ceil(depth + 1).W))
  // 连接输入输出
  io.enq.ready := count < depth.U
  io.deq.valid := count > 0.U
  io.deq.bits := mem.read(deqPtr)
  io.count := count
  // 当enq.fire()为真时，写入数据到FIFO
  when(io.enq.fire()) {
    mem.write(enqPtr, io.enq.bits)
    pointer := pointer + 1.U
    count := count + 1.U
  }
  // 当deq.fire()为真时，从FIFO读取数据
  when(io.deq.fire()) {
    pointer := pointer - 1.U
    count := count - 1.U
  }
}