动态配置接口DRP(Dynamic Reconfiguration Port)

最新推荐文章于 2025-02-24 13:45:43 发布

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最新推荐文章于 2025-02-24 13:45:43 发布

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本文链接：https://blog.csdn.net/weixin_39410955/article/details/115577434

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DRP（Dynamic Reconfiguration Port）用于动态配置MMCM或PLL，允许用户在不加载新位流的情况下更改时钟输出。文章介绍了DRP寄存器，包括MMCM时钟输出的17个寄存器配置，以及DRP状态机的结构，详细阐述了DRP State Machine与DISTROM的功能，指出它们如何控制时钟输出的频率、相位和占空比。

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文章目录

Introduction
一、DRP 寄存器
二、DRP状态机
- 状态机框图

Introduction

Reconfiguration of MMCM or PLL is performed through the DRP. The DRP provides access to the configuration bits that would normally only be initialized in the bitstream. This allows the user to dynamically change the MMCM or PLL clock outputs without loading a new bitstream. The MMCM or PLL must be held in reset during dynamic reconfiguration or must be reset after the dynamic reconfiguration changes have completed. Frequency, phase, and duty cycle can all be changed.

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