verilog向RAM中写入读取数据

`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 13:20:24 03/12/2023
// Design Name:
// Module Name: RAM_Test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module RAM_Test(
input clk,
input rst_n

				);

reg RAM_enable;
reg write_H_read_L;
reg [4:0] addr;
reg [7:0] in_data;
wire [7:0] out_data;
reg [5:0] count;//一共32个RAM。
// reg [5:0] read_count;
// reg finish_write;
// reg finish_read;

parameter read_write_size_count =10;//读10个或者写10个。

always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
RAM_enable<=1’b0;
else
RAM_enable<=1’b1; //使能RAM
end

//0–9 写入10个数据，10–19读取写入的数据。
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
count<=6’d0;
else
begin
if(RAM_enable==1’b1)//; //使能RAM
begin
if(count<6’d19)//0–19一共20个计数，0–9用于存储，10–19用于读取。
count <= count + 1’b1;
else
count <= 6’d0;
end
else
count <= 6’d0;
end

end 

always @(*)
begin
if(!rst_n )
write_H_read_L<=1’b1;
else if(RAM_enable1’b1)
begin
if(count 6’d10) //大于9以后要置低，用于读
write_H_read_L<=1’b0;
else if( count== 6’d0)//19以后切换到0,0–9用于写，置高
write_H_read_L<=1’b1;
else
write_H_read_L<=write_H_read_L;
end
else
addr <= 5’d0;
end

always @(posedge clk or negedge rst_n)
begin
if(!rst_n )
addr<=5’d0;
else if(RAM_enable1’b1)
begin
if(count5’d9 || count == 5’d19)
addr <= 5’d0;
else
addr <= addr +1’b1;
end
else
addr <= 5’d0;
end

always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
in_data<=8’d0; //要写入的从6开始
else if(RAM_enable==1’b1) //使能写的时候才开始加1
begin
if(count<8’d9)//读取用10个，写入用10个，一共20个计数。
in_data<=in_data+1’b1;
else
in_data<=in_data;
end
else
in_data<=8’d0;
end

IP_RAM your_instance_name (
.clka (clk), // input clka
.ena (RAM_enable), // input ena
.wea (write_H_read_L), // input [0 : 0] wea
.addra (addr), // input [4 : 0] addra
.dina (in_data), // input [7 : 0] dina
.douta (out_data) // output [7 : 0] douta
);

endmodule
顶层模块实例化RAM，通过ram_rdata输出读出来的数据，ena （RAM使能，高电平有效）、wea （RAM读(H)写(L)片选）、ram_addr（RAM地址）、ram_wdata（要写入的数据）由RAM的写模块提供