一、原题:
The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it’s not obvious where messages start and end. The only indication is that the first byte of each three byte message always has bit[3]=1 (but bit[3] of the other two bytes may be 1 or 0 depending on data).
We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we’ll use is to discard bytes until we see one with bit[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done).
The FSM should signal done in the cycle immediately after the third byte of each message was successfully received.
二、要求与设计
实际上就是要求找出帧头,在数据流中找出三字节中的第一个字节,bit[3]=1为第一个字节,与之后的两个字节组成一个数据帧,因此编写状态机时可以编程四个状态:
IDLE , BYTE1 ,BYTE2 ,BYTE3
但之前一直困惑我的是第一个字节 bit[3]=1,但第二个与第三个字节的bit[3]也能是1,那么bit[3]=1是不是就不能作为第一个字节的判断依据呢?但后来联系实际的硬件电路想想,一个数据流总有一个起始位,即第一个字节,不可能直接从第二个字节开始,对应着软件设计就是有一个reset的设计,因此在复位之后再对bit[3]进行检测,若bit[3]=1则代表检测到了第一个字节,否则没有检测到第一个字节
三、详细代码
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done); //
parameter IDLE = 4'b0001;
parameter BYTE1 = 4'b0010;
parameter BYTE2 = 4'b0100;
parameter BYTE3 = 4'b1000;
reg [3:0] state, nstate;
// State transition logic (combinational)
always @(*)begin
nstate = 4'd0;
case(state)
IDLE: nstate = in[3]? BYTE1:IDLE;
BYTE1:nstate = BYTE2;
BYTE2:nstate = BYTE3;
BYTE3:nstate = in[3]? BYTE1:IDLE;
default:nstate = IDLE;
endcase
end
// State flip-flops (sequential)
always @(posedge clk)begin
if(reset)begin //应加深对复位的理解
state <= IDLE;
end
else begin
state <= nstate;
end
end
// Output logic
assign done = (state == BYTE3);
endmodule
四、在此基础上再将数据打包发送,题目如下:
Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).
out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don’t-care).
五、代码如下:
注:使用时序逻辑:
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done); //
// reg [23:0] three_bytes;
parameter IDLE = 4'b0001;
parameter BYTE1 = 4'b0010;
parameter BYTE2 = 4'b0100;
parameter BYTE3 = 4'b1000;
reg [3:0] state, nstate;
// State transition logic (combinational)
always @(*)begin
nstate = 4'd0;
case(state)
IDLE: nstate = in[3]? BYTE1:IDLE;
BYTE1:begin
nstate = BYTE2;
// three_bytes[23:16] = in;
end
BYTE2:begin
nstate = BYTE3;
// three_bytes[15:8] = in;
end
BYTE3:begin
nstate = in[3]? BYTE1:IDLE;
// three_bytes[7:0] = in;
end
default:nstate = IDLE;
endcase
end
// State flip-flops (sequential)
always @(posedge clk)begin
if(reset)begin
state <= IDLE;
end
else begin
state <= nstate;
end
end
always@(posedge clk)
case(state)
IDLE:out_bytes[23:16]<=in;
BYTE1:out_bytes[15: 8]<=in;
BYTE2:out_bytes[ 7: 0]<=in;
BYTE3:out_bytes[23:16]<=in;
endcase
// Output logic
assign done = (state == BYTE3);
// assign out_bytes = done == 1'b1 ? three_bytes : 24'bz;
endmodule