习题笔记 Fsm ps2data

The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it's not obvious where messages start and end. The only indication is that the first byte of each three byte message always has bit[3]=1 (but bit[3] of the other two bytes may be 1 or 0 depending on data).

We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with bit[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done).

The FSM should signal done in the cycle immediately after the third byte of each message was successfully received.

Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).

out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don't-care).

//Fsm ps2data

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //

    // FSM from fsm_ps2
    reg [1:0]state, next_state;
    reg [23:0] datapath;
    parameter s1=2'b00, s2=2'b01,s3=2'b10,d=2'b11;       //四个状态 s1待机 检测到in[3]为1后开始跳转   s3 后进入显示done状态 注意有延迟
                                                         //done状态时 仍然检测in[3] 若为1 则跳转至s2 否则至s1 之后循环往复
                                                        //不能单独设待机状态s0 检测到1后才开始跳转s1、s2、s3 这样done会延迟一个周期
    // State transition logic (combinational)
    always @(*)
     case(state)
     s1: next_state = (in[3] ? s2 : s1);
     s2: next_state = s3;
     s3: next_state = d;
     d:  next_state = (in[3] ? s2 : s1);
     endcase  

    // State flip-flops (sequential)
    always @(posedge clk)
    begin 
      if (reset)
      state <= s1;
      else 
      state <= next_state;
    end
    // Output logic
    assign done = (state==d);
    
    
    // New: Datapath to store incoming bytes.
    always @(posedge clk)
      if(state==s1|state==d)
        datapath[23:16] <= in ;
      else if (state==s2)
        datapath[15:8] <= in ;
      else if (state==s3)
        datapath[7:0] <= in ; 

    assign out_bytes = datapath;


endmodule