HDLbits——状态机

最新推荐文章于 2023-05-16 16:50:41 发布

NDLilaco

最新推荐文章于 2023-05-16 16:50:41 发布

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分类专栏： HDLBits 文章标签： fpga开发

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状态机

1 有两个状态的摩尔型状态机

异步复位

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        // State transition logic
        case (state)
            A: next_state=in?A:B;
            B: next_state=in?B:A;
            endcase
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if (areset)
            state<=B;
        else
            state<=next_state;
    end
    assign out=(state ==B)?1'b1:1'b0;

    // Output logic
    // assign out = (state == ...);
            

endmodule

2 有两个状态的摩尔型状态机

同步复位

另一种写状态机的方式

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;
    // Fill in state name declarations
    parameter A=0, B=1;
    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin
            present_state<=B;
            out<=B;
            // Fill in reset logic
        end else begin
            case (present_state)
                A:next_state=in?A:B;
                B:next_state=in?B:A;//必须用=，阻塞
                // Fill in state transition logic
            endcase

            // State flip-flops
            present_state = next_state;   

            case (present_state)
                A:out<=A;
                B:out<=B;
                // Fill in output logic
            endcase
        end
    end

endmodule

3

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        case (state)
            ON: next_state=k?OFF:ON;
            OFF: next_state=j?ON:OFF;
        endcase        
        // State transition logic
    end

    always @(posedge clk, posedge areset) begin
        if (areset)
            state<=OFF;
        else
            state<=next_state;
        // State flip-flops with asynchronous reset
    end
    assign out = (state == ON)?ON:OFF;
endmodule

4 Fsm2s

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        case (state)
           ON:  next_state=k?OFF:ON;
           OFF:  next_state=j?ON:OFF;
        endcase          
        // State transition logic
    end

    always @(posedge clk) begin
        if (reset)
            state<=OFF;
        else 
            state<=next_state;
        // State flip-flops with synchronous reset
    end
    assign out = (state == ON)?ON:OFF;

    // Output logic
    // assign out = (state == ...);

endmodule

5 Fsm3comb

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;
    always@(*) begin
        case (state)
            A: next_state= in?B:A;
            B: next_state= in?B:C;
            C: next_state= in?D:A;
            D: next_state= in?B:C;
        endcase
    end
    assign out=(state==D)?1'b1:1'b0;                

    // State transition logic: next_state = f(state, in)
    // Output logic:  out = f(state) for a Moore state machine
endmodule

6 Fsm3onehot

5题另一种写法

module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = (state[A]&&(~in))||(state[C]&&(~in));
    assign next_state[B] = (state[D]&&(in))||(state[B]&&(in))||(state[A]&&(in));
    assign next_state[C] = (state[B]&&(~in))||(state[D]&&(~in));
    assign next_state[D] = (state[C]&&(in));

    // Output logic: 
    assign out = (state[D]==1'b1)?1'b1:1'b0;
endmodule

7 Fsm3

异步复位

module top_module(
    input clk,
    input in,
    input areset,
    output out); //

    // State transition logic
    reg [3:0] state,nextstate;
    parameter A=0, B=1, C=2, D=3;
    always @(*) begin
        case (state)
            A: nextstate=in?B:A;
            B: nextstate=in?B:C;
            C: nextstate=in?D:A;
            D: nextstate=in?B:C;
        endcase
    end
    always @(posedge clk,posedge areset) begin 
        if(areset) 
            state<=A;
        else
            state<=nextstate;
    end
    
    assign out=(state==D)?1'b1:1'b0;
endmodule

8 Fsm3

同步复位

module top_module(
    input clk,
    input in,
    input reset,
    output out); //
    reg [3:0] state,nextstate;
    parameter A=0, B=1, C=2, D=3;
    always @(*) begin
        case (state)
            A: nextstate=in?B:A;
            B: nextstate=in?B:C;
            C: nextstate=in?D:A;
            D: nextstate=in?B:C;
        endcase
    end
    always @(posedge clk) begin 
        if(reset) 
            state<=A;
        else
            state<=nextstate;
    end
    
    assign out=(state==D)?1'b1:1'b0;
endmodule

9

比较难分析

1、输入是什么？

2、现态是什么？

3、次态是什么？

4、转换条件是什么？

5、输出是什么？

在这个问题中，输入是3个传感器，现态和次态是4个水位状态（water level），转换条件是3个传感器的值是什么情况，输出是水阀的开关状态。其中水阀分两类，一类是固定水阀（nominal flow），一类是辅助水阀（supplemental flow）。

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    //三个block块并行运行
    //总共包括四种状态
    parameter L1=4'b0001,//低于s1
    B21=4'b0010,//s1 s2之间
    B23=4'b0100,
    A3=4'b1000;
    reg [3:0] state,next_state;
    
    always@(posedge clk) begin
        if(reset)
            state<=L1;
        else
            state<=next_state;
    end
    //具体状态之间的转换情况
    always@(*) begin
        case(s)
            3'b000:next_state=L1;
            3'b001:next_state=B21;
            3'b011:next_state=B23;
            3'b111:next_state=A3;
            default:next_state=L1;
        endcase
    end
    //具体每个状态对应的fr3,fr2,fr1值的情况
    always@(posedge clk) begin
        if(reset)
            {fr3,fr2,fr1}<=3'b111;
        else begin
            case(next_state)
                L1:{fr3,fr2,fr1}<=3'b111; 
                B21:{fr3,fr2,fr1}<=3'b011;
                B23:{fr3,fr2,fr1}<=3'b001;
                A3:{fr3,fr2,fr1}<=3'b000;
                default:{fr3,fr2,fr1}<=3'b111;
        endcase
        end
    end
    
    always@(posedge clk) begin
        if(reset)
            dfr<=1'b1;
        else begin
            if(next_state<state)
                dfr<=1'b1;
            else if (next_state>state)
                dfr<=1'b0;
            else 
                dfr<=dfr;
                
        end
    end
endmodule

10 Lemmings1

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right); //  

    parameter LEFT=0, RIGHT=1;
    reg state, next_state;

    always @(*) begin
        case (state) 
           LEFT: next_state=bump_left?RIGHT:LEFT;
           RIGHT: next_state=bump_right?LEFT:RIGHT;
        endcase
    // State transition logic
    end

    always @(posedge clk, posedge areset) begin
        if(areset)
            state<=LEFT;
        else
            state<=next_state;
        // State flip-flops with asynchronous reset
    end
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);

    // Output logic
    // assign walk_left = (state == ...);
    // assign walk_right = (state == ...);

endmodule

11 Lemmings2

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    
    
    
    parameter LEFT=0, RIGHT=1,fallLEFT=2,fallRIGHT=3;
    reg [1:0] state, next_state;

    always @(*) begin
        case (state) 
           LEFT: next_state=(~ground)?fallLEFT:(bump_left?RIGHT:LEFT);
           RIGHT: next_state=(~ground)?fallRIGHT:(bump_right?LEFT:RIGHT);
           fallLEFT: next_state=ground?LEFT:fallLEFT;
           fallRIGHT: next_state=ground?RIGHT:fallRIGHT;
        endcase
    // State transition logic
    end

    always @(posedge clk, posedge areset) begin
        if(areset)
            state<=LEFT;
        else
            state<=next_state;
        // State flip-flops with asynchronous reset
    end
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == fallLEFT)||(state == fallRIGHT);
endmodule

12 Lemmings2

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    
    parameter LEFT=0, RIGHT=1,fallLEFT=2,fallRIGHT=3,digLEFT=4,digRIGHT=5;
    reg [2:0] state, next_state;

    always @(*) begin
        case (state) 
            LEFT: next_state=ground?(dig?digLEFT:(bump_left?RIGHT:LEFT)):fallLEFT;    
           RIGHT: next_state=ground?(dig?digRIGHT:(bump_right?LEFT:RIGHT)):fallRIGHT;
           fallLEFT: next_state=ground?LEFT:fallLEFT;
           fallRIGHT: next_state=ground?RIGHT:fallRIGHT;
            digLEFT: next_state=ground?digLEFT:fallLEFT;   
           digRIGHT: next_state=ground?digRIGHT:fallRIGHT;
        endcase
    // State transition logic
    end

    always @(posedge clk, posedge areset) begin
        if(areset)
            state<=LEFT;
        else
            state<=next_state;
        // State flip-flops with asynchronous reset
    end
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == fallLEFT)||(state == fallRIGHT);
    assign digging = (state == digLEFT)||(state == digRIGHT);

endmodule

13 Lemmings4

难，需要计数器

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    parameter walk_left1=1,walk_right1=2,fall_left=3,fall_right=4,dig_left=5,dig_right=6,die=7;
    parameter die_time=32'd19;//20
    reg [2:0] state,next_state;
    reg [31:0]fall_count;
    //注意计数器写法
    always@(posedge clk or posedge areset) begin
        if(areset) 
            state<=walk_left1;
        else
            state<=next_state;
    end
    always @(posedge clk) begin
        if(areset)
            fall_count<=32'b0;
        else if((state==fall_left)|(state==fall_right))
            fall_count<=fall_count+32'b1;
        else
            fall_count<=32'b0;
    end
    always@(*) begin
        case(state)
            walk_left1:next_state=ground?(dig?dig_left:(bump_left?walk_right1:walk_left1)):fall_left;
            walk_right1:next_state=ground?(dig?dig_right:(bump_right?walk_left1:walk_right1)):fall_right;
            dig_left:next_state=ground?dig_left:fall_left;
            dig_right:next_state=ground?dig_right:fall_right;
            fall_left:next_state=ground?((fall_count>die_time)?die:walk_left1):fall_left;
            fall_right:next_state=ground?((fall_count>die_time)?die:walk_right1):fall_right;
            die:next_state=die;
        endcase 
    end
    assign walk_left=(state==walk_left1)&(state!=die);
    assign walk_right=(state==walk_right1)&(!state!=die);
    assign aaah=((state==fall_left)|(state==fall_right))&(!state!=die);
    assign digging=((state==dig_right)|(state==dig_left))&(!state!=die);
            
                

endmodule

14 Fsm onehot

应该是网站的一些问题

module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);
    
    assign next_state[0] = ~in & (state[0] | state[1] | state[2] | state[3] | state[4] | state[7] | state[8] | state[9]);
    assign next_state[1] = in & (state[0] | state[8] | state[9]);
    assign next_state[2] = in & state[1];
    assign next_state[3] = in & state[2];
    assign next_state[4] = in & state[3];
    assign next_state[5] = in & state[4];
    assign next_state[6] = in & state[5];
    assign next_state[7] = in & (state[6] | state[7]);
    assign next_state[8] = ~in & state[5];
    assign next_state[9] = ~in & state[6];
 
    assign out1 = state[8] | state[9];
    assign out2 = state[7] | state[9];
 
endmodule

15 Fsm ps2

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //
    
    parameter S1=0, S2=1,S3=2,DONE=3;
    reg [1:0] state, next_state;
    // State transition logic (combinational)
    always @(*) begin
        case(state)
            S1:next_state=(in[3]==1'b1)?S2:S1;
            S2:next_state=S3;
            S3:next_state=DONE;
            DONE:next_state=(in[3]==1'b1)?S2:S1;
        endcase
    end
    // State flip-flops (sequential)
    always @(posedge clk) begin
        if(reset)
            state<=S1;
        else 
            state<=next_state;
    end
    assign done=(state==DONE);
endmodule

16 Fsm ps2data

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
    parameter S1=0, S2=1,S3=2,DONE=3;
    reg [1:0] state, next_state;
    // State transition logic (combinational)
    always @(*) begin
        case(state)
            S1:next_state=(in[3]==1'b1)?S2:S1;
            S2:next_state=S3;
            S3:next_state=DONE;
            DONE:next_state=(in[3]==1'b1)?S2:S1;
        endcase
    end
    // State flip-flops (sequential)
    always @(posedge clk) begin
        if(reset)
            state<=S1;
        else 
            state<=next_state;
    end
    assign done=(state==DONE);
    always @(posedge clk) begin
        if(reset)
            out_bytes<=24'd0;
        else 
            out_bytes<={out_bytes[15:0],in};
    end

    // FSM from fsm_ps2

    // New: Datapath to store incoming bytes.

endmodule

17 Fsm serial

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    
    parameter START=0,RECEIVE=1,END=2,WAIT=3;
    reg [10:0] bit_num;
    reg [1:0] state, next_state;
    // State transition logic (combinational)
    always @(*) begin
        case(state)
            START:next_state=(in)?START:RECEIVE;
            RECEIVE:next_state=(bit_num==11'd8)?(in?END:WAIT):RECEIVE;
            END:next_state=(in)?START:RECEIVE;
            WAIT:next_state=(in)?START:WAIT;
        endcase
    end
    // State flip-flops (sequential)
    always @(posedge clk) begin
        if(reset)
            state<=START;
        else 
            state<=next_state;
    end
    assign done=(state==END);
    
    
    always @(posedge clk) begin
        if(reset)
            bit_num<=11'd0;
        else if(state==RECEIVE)
            bit_num<=bit_num+11'd1;
        else if(state==WAIT)
            bit_num<=bit_num;
        else
            bit_num<=11'd0;
    end
endmodule

18 Fsm serialdata

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
    parameter START=0,RECEIVE=1,END=2,WAIT=3;
    reg [10:0] bit_num;
    reg [1:0] state, next_state;
    // State transition logic (combinational)
    always @(*) begin
        case(state)
            START:next_state=(in)?START:RECEIVE;
            RECEIVE:next_state=(bit_num==11'd8)?(in?END:WAIT):RECEIVE;
            END:next_state=(in)?START:RECEIVE;
            WAIT:next_state=(in)?START:WAIT;
        endcase
    end
    // State flip-flops (sequential)
    always @(posedge clk) begin
        if(reset)
            state<=START;
        else 
            state<=next_state;
    end
    assign done=(state==END);
    
    
    always @(posedge clk) begin
        if(reset)
            bit_num<=11'd0;
        else if(state==RECEIVE)
            bit_num<=bit_num+11'd1;
        else if(state==WAIT)
            bit_num<=bit_num;
        else
            bit_num<=11'd0;
    end
    
    always @(posedge clk) begin
        if(reset)
            out_byte<=8'd0;
        else if((state == RECEIVE) && (bit_num<11'd8))
            out_byte[bit_num]<=in;
        else
            out_byte<=out_byte;
    end

endmodule

19 Fsm serialdp

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //

    // Modify FSM and datapath from Fsm_serialdata

    parameter START=0,RECEIVE=1,END=2,WAIT=3;
    reg [7:0] bit_num;
    reg [1:0] state, next_state;
    // State transition logic (combinational)
    always @(*) begin
        case(state)
            START:next_state=(in)?START:RECEIVE;
            RECEIVE:next_state=(bit_num==11'd9)?(in?(odd?END:START):WAIT):RECEIVE;
            END:next_state=(in)?START:RECEIVE;
            WAIT:next_state=(in)?START:WAIT;
        endcase
    end
    // State flip-flops (sequential)
    always @(posedge clk) begin
        if(reset)
            state<=START;
        else 
            state<=next_state;
    end
    assign done=(state==END);
    
    
    always @(posedge clk) begin
        if(reset)
            bit_num<=11'd0;
        else if(state==RECEIVE)
            bit_num<=bit_num+11'd1;
        else if(state==WAIT)
            bit_num<=bit_num;
        else
            bit_num<=11'd0;
    end
    
    always @(posedge clk) begin
        if(reset)
            out_byte<=8'd0;
        else if((state == RECEIVE) && (bit_num<8'd8))
            out_byte[bit_num]<=in;
        else
            out_byte<=out_byte;
    end

    // New: Add parity checking.
    wire odd;
    parity parity1(clk,(state!=RECEIVE),in,odd);

endmodule

20 考试/ece241 2013 Q8

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    parameter S0=0,S1=1,S2=2;
    reg [1:0] state,next_state;
    always @(*) begin
        case(state) 
            S0:next_state=(x?S1:S0);
            S1:next_state=(x?S0:S2);
            S2:next_state=(x?S1:S0);
        endcase
    end
    
    always@(posedge clk or negedge aresetn) begin
        if(~aresetn) 
            state<=S0;
        else
            state<=next_state;
    end
    assign z=(state==S2)&&x;
    

endmodule

少了一个在这加

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    reg [3:0] state,next_state;
    parameter d1=1,d2=2,d3=3,d4=4,d5=5,d6=6,d7=7,disc1=8,flag1=9,err1=10;
    always@(*) begin
        case(state)
            d1:next_state=in?d2:d1;
            d2:next_state=in?d3:d1;
            d3:next_state=in?d4:d1;
            d4:next_state=in?d5:d1;
            d5:next_state=in?d6:d1;
            d6:next_state=in?d7:disc1;
            d7:next_state=in?err1:flag1;
            disc1:next_state=in?d2:d1;
            flag1:next_state=in?d2:d1;
            err1:next_state=in?err1:d1;
        endcase
    end
    
    always@(posedge clk) begin
        if(reset)
            state<=d1;
        else
            state<=next_state;
    end
    assign disc=(state==disc1);
    assign flag=(state==flag1);
    assign err=(state==err1);

endmodule

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    parameter S0=0,S1=1,S2=2;
    reg [1:0] state,next_state;
    always @(*) begin
        case(state) 
            S0:next_state=(x?S1:S0);
            S1:next_state=(x?S1:S2);
            S2:next_state=(x?S1:S0);//注意当x=1/0时该转到哪个状态
        endcase
    end
    
    always@(posedge clk or negedge aresetn) begin
        if(~aresetn) 
            state<=S0;
        else
            state<=next_state;
    end
    assign z=((state==S2)&&x);
    

endmodule

22 Exams/ece241 2014 q5a

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
     parameter A=0,B=1,C=2,D=3;
    reg [2:0] state,next_state;
    always @(*) begin
        case(state)
            A:next_state=x?B:A;
            B:next_state=x?D:C;
            C:next_state=x?D:C;//C、D是判断第一个为1后，后面直接反，因此当x=1时，为D（此时D输出为0）
            D:next_state=x?D:C;
        endcase
     end   
    
    
    always@(posedge clk or posedge areset) begin
        if(areset) 
            state<=A;
        else
            state<=next_state;
    end
    always @(*) begin
        if(state==A)
            z=1'b0;
        else if(state==B)
            z=1'b1;
        else if(state==C)
            z=1'b1;
        else if(state==D)
            z=1'b0;
     end  
endmodule

23Exams/ece241 2014 q5b

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    parameter A=0,B=1;
    reg [1:0] state,next_state;
    always @(*) begin
        case(state)
            A:next_state=x?B:A;
            B:next_state=B;
        endcase
     end   
    
    
    always@(posedge clk or posedge areset) begin
        if(areset) 
            state<=A;
        else
            state<=next_state;
    end
    always @(*) begin
        if(state==A)
            z=x;
        else if(state==B)
            z=(~x);
     end  
    

endmodule

24 Exams/2014 q3fsm

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
    reg [1:0] ww,cout;
    reg [1:0] state,next_state;
    parameter A=1,B=2;
    
    always @(posedge clk) begin
        if(reset)
            state<=A;
        else
            state<=next_state;
    end
    always @(*) begin
        case(state)
            A:next_state=s?B:A;
            B:next_state=B;
        endcase
    end
    
    always @(posedge clk) begin
        if(reset)
            cout<=2'b0;
        else if(state==B) begin
            if (cout==2'd2)
                cout<=2'b0;
            else
                cout<=cout+2'b1;
        end
        else
            cout<=2'b0;
    end
    
    always @(posedge clk) begin
        if(reset)
            ww<=2'b0;
        else if(state==B )
                ww<={ww[0],w};
        else
                ww<=2'b0;
    end
    always @(posedge clk) begin
        if(reset)
            z<=1'b0;
        else if((state==B)&(cout==2'd2)&(({ww,w}==3'b110)|({ww,w}==3'b101)|({ww,w}==3'b011)))
                z<=1'b1;
        else
                z<=1'b0;
    end

endmodule

26Exams/2014 q3bfsm

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);
    parameter S0=3'b000,S1=3'b001,S2=3'b010,S3=3'b011,S4=3'b100;
    reg [2:0] state,next_state;
    
    always@(*) begin
        case(state)
            S0:next_state=x?S1:S0;
            S1:next_state=x?S4:S1;
            S2:next_state=x?S1:S2;
            S3:next_state=x?S2:S1;
            S4:next_state=x?S4:S3;
       endcase
    end
    always@(posedge clk) begin
        if(reset)
            state<=S0;
        else
            state<=next_state;
    end
    assign z=(state==S3)||(state==S4);

endmodule

27Exams/2014 q3c

module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);
    
    parameter S0=3'b000,S1=3'b001,S2=3'b010,S3=3'b011,S4=3'b100;
    reg [2:0] next_state;
    always@(*) begin
        case(y)
            S0:next_state=x?S1:S0;
            S1:next_state=x?S4:S1;
            S2:next_state=x?S1:S2;
            S3:next_state=x?S2:S1;
            S4:next_state=x?S4:S3;
       endcase
    end
    assign Y0=next_state[0];
    assign z=(y==S3)||(y==S4);


endmodule

28Exams/m2014 q6b

module top_module (
    input [3:1] y,
    input w,
    output Y2);
    reg [2:0] next_state;
    parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100,F=3'b101;
    always@(*) begin
        case(y) 
            A:next_state=w?A:B;
            B:next_state=w?D:C;
            C:next_state=w?D:E;
            D:next_state=w?A:F;
            E:next_state=w?D:E;
            F:next_state=w?D:C;
        endcase
    end
    assign Y2=next_state[1];

endmodule

29Exams/m2014 q6c

module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);
    
    reg [6:1] next_state;
    parameter A=3'b000001,B=3'b000010,C=3'b000100,D=3'b001000,E=3'b010000,F=3'b100000;
    always@(*) begin
        case(y) 
            A:next_state=w?A:B;
            B:next_state=w?D:C;
            C:next_state=w?D:E;
            D:next_state=w?A:F;
            E:next_state=w?D:E;
            F:next_state=w?D:C;
        endcase
    end
    assign Y2=y[1]&&(~w);//怎么能到Y2状态（B）
    assign Y4=(y[2]&&(w))||(y[3]&&(w)) ||(y[5]&&(w))||(y[6]&&(w));//怎么能到Y2状态（D）
endmodule

30Exams/m2014 q6

简单

31Exams/2012 q2fsm

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    input w,
    output z
);
    reg [2:0] state,next_state;
    parameter A=0,B=1,C=2,D=3,E=4,F=5;
    
    always@(*) begin
        case(state)
            A:next_state=w?B:A;
            B:next_state=w?C:D;
            C:next_state=w?E:D;
            D:next_state=w?F:A;
            E:next_state=w?E:D;
            F:next_state=w?C:D;
        endcase
    end
    always@(posedge clk) begin
        if(reset)
            state<=A;
        else
            state<=next_state;
    end
    assign z=(state==E)||(state==F);

endmodule

32Exams/2012 q2b

module top_module (
    input [5:0] y,
    input w,
    output Y1,
    output Y3
);
    reg [5:0] next_state;
    parameter A=6'b000001,B=6'b000010,C=6'b000100,D=6'b001000,E=6'b010000,F=6'b100000;
    
    always@(*) begin
        case(y)
            A:next_state=w?B:A;
            B:next_state=w?C:D;
            C:next_state=w?E:D;
            D:next_state=w?F:A;
            E:next_state=w?E:D;
            F:next_state=w?C:D;
        endcase
    end
    
    assign Y1=y[0]&&w;
    assign Y3=(y[1]&& ~w)||(y[2]&& ~w)||(y[4]&& ~w)||(y[5]&& ~w);

endmodule

33 Exams/2013 q2afsm

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
); 
   reg [3:1] state,next_state;
    parameter A=3'b000,B=3'b001,C=3'b010,D=3'b100;
    
    always @(*) begin
        case(state)
            A:
                casez(r)
                    3'b000:next_state=A;
                    3'bzz1:next_state=B;
                    3'bz1z:next_state=C;
                    3'b1zz:next_state=D;
                    default:next_state=A;
                endcase
            B:next_state=r[1]?B:A;
            C:next_state=r[2]?C:A;
            D:next_state=r[3]?D:A;
        endcase
           
    end
    always@(posedge clk) begin
        if(~resetn)
            state<=A;
        else
            state<=next_state;
    end
    always @(*) begin
       g=3'b000;
        case(state)
            B:g=3'b001;
            C:g=3'b010;
            D:g=3'b100;
        endcase
    end
endmodule

34 注意可用状态机做完，注意状态机画法

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    reg [4:0]state,next_state;
    parameter IDEL=0,FHIGH=1,X1=2,X2=3,X3=4,y1=5,y2=6,Ghigh=7,Glow=8;
    reg yy;
    always @(posedge clk) begin
        if(~resetn)
            state<=IDEL;
        else
            state<=next_state;
    end
    always @(*) begin
        case(state)
            IDEL:next_state=FHIGH;
            FHIGH:next_state=X1;
            X1:next_state=x?X2:X1;
            X2:next_state=x?X2:X3;
            X3:next_state=x?y1:X1;
            y1:next_state=y?Ghigh:y2;
            y2:next_state=y?Ghigh:Glow;
            Ghigh:next_state=Ghigh;
            Glow:next_state=Glow;
            default:next_state=IDEL;
        endcase
    end
    assign f=(state==FHIGH);
    assign g=(state==Ghigh)||(state==y1)||(state==y2);
            

endmodule