联发科序列检测题 110序列选择器

Mealy型

module sqe_de_MTK_2018(
        input clk,
        input rst_n,
        input in,
        output out
    
    );
    
    parameter st0 = 2'b00;
    parameter st1 = 2'b01;
    parameter st2 = 2'b10;
    reg [1:0] state = st0,next_state;
    reg out_b;
     
    always@(posedge clk or negedge rst_n)begin
        if(rst_n)begin
            state <= st0;
        end
        else begin
            state <= next_state;
        end
    end
    
    always@(*)begin
        case(state)
            st0:
                if(in == 1'b1)begin
                    next_state <= st1;
                end
                else begin
                    next_state <= st0;
                end
            st1:
                if(in == 1'b1)begin
                    next_state <= st2;
                end
                else begin
                    next_state <= st0;
                end
            st2:
                if(in == 1'b1)begin
                    next_state <= st2;
                end
                else begin
                    next_state <= st0;
                end
        endcase
    end
    
    always@(posedge clk or negedge rst_n)begin
        if(rst_n)begin
            out_b <= 1'b0;
        end
        else begin
            out_b <= 1'b0;
            case(state)
                st0:out_b <= 1'b0;
                st1:out_b <= 1'b0;
                st2:
                    if(in == 1'b1)
                        out_b <= 1'b0;
                    else
                        out_b <= 1'b1;
            endcase
        end
    end
    reg out_a;
    always@(posedge clk or negedge rst_n) begin
        if(rst_n)
            out_a = 0;
        else
            out_a = ~in & state[1];
    end
    assign out = out_b;
    wire out_1;
    assign out_1 = ~in & state[1];

endmodule

从图中可以看出，out_1比out_b，out_a提前一个时钟周期