HDLBits: Exams/ece241 2014 q5a 刷题记录

You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires an asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted.

For example:

时序例图上的数据按照二进制正常表示方法即为：

input(x)  : 011_0100

output(z): 100_1100

分析：

output 是负数的二进制补码或者是 0。根据负数补码规则，负数原码最高位（符号位）不变，其余位取反得到反码，反码加 1 得到补码。通过观察，本题原码转换为补码有这样一个简单规律：从最低位开始一直到遇到的第一个 1 （例如 100）保持不变（仍为 100），之后一律按位取反。依照这样的规律可以创建一个 moore 状态机，状态机包括空闲态、指示态、P 态、和 N 态。

module top_module (
    input clk,
    input areset,
    input x,
    output reg z
  );

  parameter IDLE     = 2'h0;
  parameter SIGNED   = 2'h1;
  parameter BIT_P    = 2'h2;
  parameter BIT_N    = 2'h3;

  reg [1:0] cur_state, nxt_state;

  always @(*)
  begin
    case(cur_state)

      IDLE:
      begin
        nxt_state = x?SIGNED:IDLE;
      end

      SIGNED:
      begin
        nxt_state = x?BIT_N:BIT_P;
      end

      BIT_P:
      begin
        nxt_state = x?BIT_N:BIT_P;
      end

      BIT_N:
      begin
        nxt_state = x?BIT_N:BIT_P;
      end

      default:
      begin
        nxt_state = IDLE;
      end

    endcase
  end

  always @(posedge clk, posedge areset)
  begin
    if(areset)
      cur_state <= IDLE;
    else
      cur_state <= nxt_state;
  end

  always @(*)
  begin
    case(cur_state)

      IDLE:
      begin
        z = 1'h0;
      end

      SIGNED:
      begin
        z = 1'h1;
      end

      BIT_P:
      begin
        z = 1'h1;
      end

      BIT_N:
      begin
        z = 1'h0;
      end

      default:
      begin
        z = 1'h0;
      end

    endcase
  end

endmodule