Verilog异步复位同步释放

小鼹鼠骑士

已于 2023-05-01 06:11:25 修改

阅读量144

点赞数

文章标签： fpga开发

于 2022-09-11 07:50:54 首次发布

本文链接：https://blog.csdn.net/weixin_43570886/article/details/126801913

版权

`timescale 1ns/1ns


module ybfwtbsf(
input  wire clk,
input  wire rst_n,
input  wire d,
output reg dout
 );
 
reg rst0,rst1;
always @ (posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		rst0 <= 0;
	    rst1 <= 0;
	end
	else begin
		rst0 <= 1; 
		rst1 <= rst0; 
	end
end
 
            
always @ (posedge clk or negedge rst1)begin
        if(!rst1) begin
			dout <= 1'b0;
		end
        else begin 
 			dout <= d; 
		end		 
end            

            
endmodule