三种256MB SPIFLASH的高性能模式和软复位学习笔记

转载请标明出处 https://blog.csdn.net/weixin_43685170 ，作者：HyunYew.

WINBONE

winbone 的 W25Q256FV

CONTINUE READ MODE

W25Q256FV有一个 CONTINUE READ MODE , 支持无command的数据读取（只有ADDR+DATA），为读取提供更快的速度。

The Fast Read Dual I/O

The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the“Continuous Read Mode” bits (M7-0) after the input Address bits (A23/A31-0), as shown in Figure 22a.The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BBh instruction code, as shown in Figure 22b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFFFh/FFFFFh on IO0 for the next instruction (16/20 clocks), to ensure M4 = 1 and return the device to normal operation.

The Fast Read Quad I/O

The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23/A31-0), as shown in Figure 24a. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh instruction code, as shown in Figure 24b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh/3FFh on IO0 for the next instruction (8/10 clocks), to ensure M4 = 1 and return the device to normal operation.

winbone的W25Q系列FLASH只支持24bit ADDR 模式；

SOFTWARE RESET

The W25Q256FV can be reset to the initial power-on state by a software Reset sequence, either in SPI mode or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset (99h). If the command sequence is successfully accepted, the device will take approximately 30uS (tRST) to reset. No command will be accepted during the reset period.

EON

EON的EN25QH256

PERFORMANCE ENHANCE MODE

EON的EN25Q只支持4bit command(QPI) 模式下的performance enhance mode

In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh) instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. And afterwards CS# is raised, the system then will escape from performance enhance mode and return to normal operation.
Sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24- bit address interleave on DQ3, DQ2, DQ1 and DQ0 -> performance enhance toggling bit P[7:0] -> 4 dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 till CS# goes high -> CS# goes low (reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit or 32-bit random access address (depending on mode state)

需要6个dummy clk，前两个是M7-M0的一个byte。

（Note:

1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F
2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
3. Please note the above address cycles are based on 3-byte address mode, for 4-byte address mode, the address cycles will be increased.
4. performance enhance mode need to use qual reset-enable(66H）and qual reset (99H) COMMOMD )

SOFTWARE RESET

The Reset operation is used as a system (software) reset that puts the device in normal operating Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). To reset the EN25QH256 the host drives CS# low, sends the Reset-Enable command (66h), and drives CS# high. Next, the host drives CS# low again, sends the Reset command (99h), and drives CS# high. The Reset operation requires the Reset-Enable command followed by the Reset command. Any command other than the Reset command after the Reset-Enable command will disable the ResetEnable
(Note:

1. Reset-Enable (RSTEN) (66h) and Reset (RST) (99h) commands need to match standard SPI or
   EQPI (Quad) mode.
2. Continue (Enhance) EB mode need to use quad Reset-Enable (RSTEN) (66h) and quad Reset (RST)
   (99h) commands.
3. If user is not sure it is in SPI or Quad mode, we suggest to execute sequence as follows:
   Quad Reset-Enable (RSTEN) (66h) -> Quad Reset (RST) (99h) -> SPI Reset-Enable (RSTEN) (66h)
   -> SPI Reset (RST) (99h) to reset.
4. The reset command could be executed during embedded program and erase process, EQPI mode
   and Continue EB mode to back to SPI mode.
5. This flow cannot release the device from Deep power down mode.
6. The Status Register Bit and Information register Bit will reset to default value after reset done.
7. If user reset device during erase, the embedded reset cycle software reset latency will take about
   28us in worst case.
   )

MXIC

MXIC 的MX25L25635E

PERFORMANCE ENHANCE MODE

参考EON的PERFORMANCE ENHANCE MODE；

RESET

MX25L25635E只有HARD RESET ,没有softtware reset

总结：当芯片在SFC模式下运行时，与FLASH的交流过程中，有因为断电或者芯片重启的可能导致重新上电后的芯片不知道FLASH现在正在运行什么MODE（如1/4bit command模式、3/4 byte ADDR 模式、performance enhance mode/continue read mode(无法输入instruction) )，这时芯片需要 将FLASH初始化但又不能 发送过多指令造成MASKROM的浪费，此时可以发送N个FFH去初始化FLASH；
（4wire FFFFFF可以使M7-M0为退continue mode ，下一个instruction 接收为FFH时是EX-QPI指令（退出4bitcommand mode）这时FLASH就Reset成初始的1bit commmond 状态）。