这题没啥好说的,和之前的一样牛客网刷题记录——序列检测器,直接放代码。
`timescale 1ns/1ns
module sequence_test1(
input wire clk ,
input wire rst ,
input wire data ,
output reg flag
);
parameter IDLE = 5'b00001,
S1 = 5'b00010,
S2 = 5'b00100,
S3 = 5'b01000,
S4 = 5'b10000;
reg [4:0]state,next_state;
always@(posedge clk or negedge rst)
if(~rst)
state <= IDLE;
else
state <= next_state;
always@(*)
if(~rst)
next_state <= IDLE;
else
case(state)
IDLE:next_state <= (data)?S1:IDLE;
S1:next_state <= (~data)?S2:IDLE;
S2:next_state <= (data)?S3:IDLE;
S3:next_state <= (data)?S4:IDLE;
S4:next_state <= IDLE;
default:next_state <= IDLE;
endcase
always@(posedge clk or negedge rst)
if(~rst)
flag <= 1'b0;
else if((state==S4) && data)
flag <= 1'b1;
else
flag <= 1'b0;
endmodule