用verilog来写一个寄存器并添加延时

 

 

 

 

`timescale  1ns/1ps
module test_reg();
reg clk;
reg rst_n;
parameter DW=32;
reg [DW-1:0] qout_r;
reg [DW-1:0] dnxt;
reg lden;
wire [DW-1:0]qout;

initial begin
   clk <= 0;
   forever #5 clk <= ~clk; 
end

initial begin
    rst_n  <= 0;
	repeat(10)  @(posedge clk);
	rst_n <= 1;
end

initial begin
   lden <= 0;
	repeat(20)  @(posedge clk);
	lden <= 1;
end
always @(posedge clk or negedge rst_n)
begin
  if (rst_n == 1'b0)
   dnxt <= 32'b0;
  else 
	dnxt <= dnxt + 1;	
end

always @(posedge clk or negedge rst_n)
begin : DFFLRS_PROC
  if (rst_n == 1'b0)
    qout_r <= {DW{1'b1}};
  else if (lden == 1'b1)
    qout_r <= #1 dnxt;
end

assign qout = qout_r;

endmodule