Exams/review2015 fsmseq

最新推荐文章于 2023-12-19 18:51:08 发布

我不吃辣条

最新推荐文章于 2023-12-19 18:51:08 发布

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分类专栏： HDLBITS 文章标签： verilog

本文链接：https://blog.csdn.net/weixin_44101336/article/details/122336300

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![在这里插入图片描述](https://img-blog.csdnimg.cn/32524b85a3674411874353fbda640e8c.png?x-oss-process=image/watermark,type_d3F5LXplbmhlaQ,shadow_50,text_Q1NETiBA5oiR5LiN5ZCD6L6j5p2h,size_20,color_FFFFFF,t_70,g_se,x_16
其实这里之前我犯了一个错把data和state对应起来了，其实是state延迟了一个周期的；可以理解成在data在输入第一个1时那时候处在s0状态，然后在下一个周期才进行跳转；

米利型异步：会在current_state ==s3的时候直接改变
在这里插入图片描述

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
    
	parameter S0=0, S1=1, S2=2, S3=3;
    reg [2:0] state, state_next;
    
    always @(*) begin
        case (state)
            S0 : begin 
                if (data) state_next = S1;
                else      state_next = S0;
            end
            S1 : begin 
                if (data) state_next = S2;
                else      state_next = S0;
            end
            S2 : begin 
                if (data) state_next = S2;
                else      state_next = S3;
            end
            S3 : begin 
                if (data) state_next = S3;
                else      state_next = S0;
            end

            default : state_next = S0; 
        endcase
    end
    
    always @(posedge clk)
        begin
            if (reset) state <= S0;
            else state <= state_next;
        end 
    
    reg start_shifting1;
    always @(*)
        if (reset)
            start_shifting1<=0;
        
    else begin
    		start_shifting1 = start_shifting1?1:(state == S3 && data==1);
        end
    assign start_shifting=start_shifting1;
        
endmodule

米利型同步：会在current_state==s3的下一个时钟沿生效；
在这里插入图片描述

    always @(posedge clk)
        if (reset)
            start_shifting1<=0;
        
    else begin
    		start_shifting1 = start_shifting1?1:(state == S3 && data==1);
        end
    assign start_shifting=start_shifting1;

摩尔型状态机：在current_state==s4时候立即发生变化；
在这里插入图片描述

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
    
	parameter S0=0, S1=1, S2=2, S3=3;
    reg [2:0] state, state_next;
    
    always @(*) begin
        case (state)
            S0 : begin 
                if (data) state_next = S1;
                else      state_next = S0;
            end
            S1 : begin 
                if (data) state_next = S2;
                else      state_next = S0;
            end
            S2 : begin 
                if (data) state_next = S2;
                else      state_next = S3;
            end
            S3 : begin 
                if (data) state_next = S4;
                else      state_next = S0;
            end
            S4 : begin
                state<=s4;  
            end

            default : state_next = S0; 
        endcase
    end
    
    always @(posedge clk)
        begin
            if (reset) state <= S0;
            else state <= state_next;
        end 
    assign start_shifting=start
    
   /* reg start_shifting1;
    always @(posedge clk)
        if (reset)
            start_shifting1<=0;
        
    else begin
    		start_shifting1 = start_shifting1?1:(state == S3 && data==1);
        end
    assign start_shifting=start_shifting1;*/
        
endmodule