手写一个序列发生器

题目：
手写一个10110序列发生器
方法1、通过循环移位方式实现
方法2、通过状态机来实现
废话少说上代码：
方法1：

module sequence_gen(
    input wire clk,
    input wire rstn,
    //input wire [4:0] seq_in,
    output reg seq
);
parameter seq_in=5'b01101;
reg [4:0] shift_reg;
always @(posedge clk or negedge rstn) begin
    if(~rstn) begin
        shift_reg<=seq_in;
    end
    else begin
        shift_reg<={shift_reg[3:0],shift_reg[4]};
    end

end
always @(posedge clk or negedge rstn) begin
    if(~rstn) begin
        seq<='b0;
    end
    else begin
        seq<=shift_reg[4];
    end

end
endmodule

方法2：

module sequence_gen_fsm(
    input wire clk,
    input wire rstn,
    //input wire [4:0] seq_in,
    output reg seq
);
parameter seq_in=5'b01101;
reg [4:0] shift_reg;
reg [4:0] current_state,next_state;
parameter s1=4'b0000;
parameter s2=4'b0001;
parameter s3=4'b0010;
parameter s4=4'b0011;
parameter s5=4'b0100;
parameter idle=4'b0101;

always @(posedge clk or negedge rstn) begin
    if(~rstn)
        current_state<=idle;
    else begin
        current_state<=next_state;
    end
end

always @(*) begin
    case (current_state)
        idle:begin 
            if(~rstn)
                next_state<=idle;
            else 
                next_state<=s1;
        end
        s1:next_state<=s2;
        s2:next_state<=s3;
        s3:next_state<=s4;
        s4:next_state<=s5;
        s5:next_state<=idle;
        default:next_state<=idle; 
    endcase
end
always @(*) begin
   case (next_state)
        idle:seq<='bz;
        s1:seq<=0;
        s2:seq<=1;
        s3:seq<=1;
        s4:seq<=0;
        s5:seq<=1;
        default:seq<='b0;
    endcase
end
endmodule

tb:

`timescale 1ns / 1ps
module tb_seq();
reg clk;
reg rstn;
wire req1,req2;
parameter perd = 20;
initial begin
    rstn=1;
    clk=1;
    #20 rstn =0;
    #20 rstn =1;
end

always #(perd/2) clk =~clk;


sequence_gen sequence_gen_inst1(
    .clk(clk),
    .rstn(rstn),
    //input wire [4:0] seq_in,
    .seq(seq1)
);


sequence_gen_fsm sequence_gen_fsm_inst1(
    .clk(clk),
    .rstn(rstn),
    //input wire [4:0] seq_in,
    .seq(seq2)
);
endmodule