Verilog HDL实现0Hz-9999Hz方波频率计

IP编程实现频率计

 频率计IP编程实现后，鄙人一直想着用Verilog HDL编程实现频率计，奈何HDL入门不易，学了3天才懵懵懂懂地编出频率计，以下是我能想到频率计最简单的实现代码，动态数码管显示的参考了一些资料，仅用一个module实现0Hz-9999Hz方波频率计，具体细节方面有待改进和优化。
编程思路与IP编程类似，具体方法请看注释。

//  声明
//  Created by Livion on 2020/9/8.
//  Copyright © 2020 Livion. All rights reserved.

Verilog HDL实现

`timescale 1ns / 1ps


module bcd_2_7seg(
        input square, //输入的方波 
        input wire clk, //FPGA晶振
        output reg [6:0] seg, //7段数码管
        output reg [3:0] s //位选
        );
    reg [3:0] s1_data; //个位	
    reg [3:0] s2_data; //十位
    reg [3:0] s3_data; //百位
    reg [3:0] s4_data; //千位

    //4个寄存器保留频率数
    reg [3:0] lockdata1; //个位
    reg [3:0] lockdata2; //十位
    reg [3:0] lockdata3; //百位
    reg [3:0] lockdata4; //千位
    
    
    reg [26:0] count;  //分频器需要的寄存器，100MHZ共27位宽
    reg flag;			//1Hz 
    reg flag1;			//个位进十位
    reg flag2;			//十位进百位
    reg flag3;			//百位进千位
    
	//分频函数，将100MHz晶振分频为1Hz，以flag为标志位
    always @(posedge clk)begin 
    if(count == 27'd99999999)begin //1秒钟100M次
    flag <= 0;
    count<=27'b0;
    end
    else begin
    count<=count+27'b1;
    flag <=1;
    end
    end
    
	//个位计数器
    always@(posedge square or negedge flag)begin
    if(!flag)
    s1_data<=4'b0000;
    else begin
    if(s1_data==4'b1001)begin
    s1_data<=4'b0000;
    flag1<=1;
    end
    else begin
    s1_data <= s1_data+4'b1;
    flag1<=0;
    end
    end
    end
    
	//十位计数器
    always@(posedge flag1 or negedge flag)begin
    if(!flag)
    s2_data<=4'b0000;
    else begin
    if(s2_data==4'b1001)begin
    s2_data<=4'b0000;
    flag2<=1;
    end
    else begin
    s2_data <= s2_data+4'b1;
    flag2<=0;
    end
    end
    end
    
	//百位计数器
    always @ (posedge flag2 or negedge flag)begin
    if(!flag)
    s3_data<=4'b0000;
    else begin
    if(s3_data==4'b1001)begin
    s3_data<=4'b0000;
    flag3<=1;
    end
    else begin
    s3_data <= s3_data+4'b1;
    flag3<=0;
    end
    end
    end
    
	//千位计数器
    always @ (posedge flag3 or negedge flag)begin
    if(!flag)
    s4_data<=4'b0000;
    else begin
    if(s4_data==4'b1001)
    s4_data<=4'b0000;
    else 
    s4_data <= s4_data+4'b1;
    end
    end
    
    reg [3:0] data; //各位数据
    reg [18:0] times; 
    
    initial times = 0;   
    initial s = 4'b0001; //初始化位选
    
	//一秒钟将所存的频率送给数码管
    always @ (negedge flag)begin
    lockdata1<=s1_data;
    lockdata2<=s2_data;
    lockdata3<=s3_data;
    lockdata4<=s4_data;
    end
    
	//4位数码动态扫描 低电平有效
    always @ (posedge clk)
        begin
        times <= times + 19'b1;
        case (times)
            19'd000000: begin s <= 4'b1110; data <= lockdata1; end
            19'd100000: begin s <= 4'b1101; data <= lockdata2; end
            19'd200000: begin s <= 4'b1011; data <= lockdata3; end
            19'd300000: begin s <= 4'b0111; data <= lockdata4; end
        endcase
        if(times == 400000)
            times <= 19'b0;
        end
    
	//7段数码管翻译
    always @ (posedge clk)
    begin
        case(data)
            4'b0000: seg = 7'b1000000;    //0
            4'b0001: seg = 7'b1111001;    //1
            4'b0010: seg = 7'b0100100;    //2
            4'b0011: seg = 7'b0110000;    //3
            4'b0100: seg = 7'b0011001;    //4
            4'b0101: seg = 7'b0010010;    //5
            4'b0110: seg = 7'b0000010;    //6
            4'b0111: seg = 7'b1111000;    //7
            4'b1000: seg = 7'b0000000;    //8
            4'b1001: seg = 7'b0010000;    //9
            4'b1010: seg = 7'b0001000;    //A
            4'b1011: seg = 7'b0000011;    //b
            4'b1100: seg = 7'b1000110;    //C
            4'b1101: seg = 7'b0100001;    //d
            4'b1110: seg = 7'b0000110;    //E
            4'b1111: seg = 7'b0001110;    //F
        endcase
    end
endmodule

Basys3约束文件如下：

set_property IOSTANDARD LVCMOS33 [get_ports clk]
#set_property IOSTANDARD LVCMOS33 [get_ports oneHz]
set_property IOSTANDARD LVCMOS33 [get_ports square]
set_property IOSTANDARD LVCMOS33 [get_ports {s[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN U2 [get_ports {s[0]}]
set_property PACKAGE_PIN U4 [get_ports {s[1]}]
set_property PACKAGE_PIN V4 [get_ports {s[2]}]
set_property PACKAGE_PIN W4 [get_ports {s[3]}]
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
set_property PACKAGE_PIN W5 [get_ports clk]
set_property PACKAGE_PIN A16 [get_ports square]
#set_property PACKAGE_PIN B15 [get_ports oneHz]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]

实现效果

动图