HDLBit-全加器

三位全加器
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
genvar i;
generate
for(i=0;i<3;i++)
begin:lll
if(i == 0)
full_addr A(.a(a[i]),.b(b[i]),.cin(cin),.cout(cout[i]),.sum(sum[i]));
else
full_addr A(.a(a[i]),.b(b[i]),.cin(cout[i-1]),.cout(cout[i]),.sum(sum[i]));
end
endgenerate
endmodule
module full_addr(input a,b,cin,output cout,sum);
assign cout = (a&b)|(a&cin)|(b&cin);
assign sum = a^bcin;
endmodule