HDLBit学习笔记（三）

最新推荐文章于 2023-08-17 16:25:28 发布

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最新推荐文章于 2023-08-17 16:25:28 发布

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文章标签：学习笔记

本文链接：https://blog.csdn.net/gakkif/article/details/130649065

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Shift4

Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.

areset: Resets shift register to zero.//异步复位，上升沿有效
load: Loads shift register with data[3:0] instead of shifting.//Load为高时，赋值输出
ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears).//使能移位
q: The contents of the shift register.//输出

If both the load and ena inputs are asserted (1), the load input has higher priority.

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    always @(posedge clk or posedge areset) begin
        if(areset)
            q<=4'd0;
        else begin 
        	if(load)
            	q<=data;
            else if(ena)
            	q<=q>>1;
        end
    end
            
endmodule

注意：if···else语句优先级关系，第一个if具有最高优先级，最后一个else if具有最低优先级，题干中load优先级大于ena

Shift18

Build a 64-bit arithmetic shift register//算术右移, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.

An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this case) instead of zero as done by a logical right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed and preserves the sign, so that arithmetic right shift divides a signed number by a power of two.

There is no difference between logical and arithmetic left shifts.

load: Loads shift register with data[63:0] instead of shifting.
ena: Chooses whether to shift.
amount: Chooses which direction and how much to shift.
- 2'b00: shift left by 1 bit.
- 2'b01: shift left by 8 bits.
- 2'b10: shift right by 1 bit.
- 2'b11: shift right by 8 bits.
q: The contents of the shifter.

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    always @(posedge clk) begin
        if(load) begin
            q<=data;
        end
        else if(ena)begin
            if(amount==2'b00) begin
                q<=q<<1;
            end
            if(amount==2'b01) begin
                q<=q<<8;
        	end	
            if(amount==2'b10) begin
                q<={q[63],q[63:1]};
            end
            if(amount==2'b11) begin
                q<={{8{q[63]}},q[63:8]};
            end
        end
    end
endmodule

注意：逻辑移位和算术移位的区别

算术左移=逻辑左移：右侧均添0
逻辑右移：左侧均添0
算术右移：最高位取决于符号位，符号位为1添1，符号位为0添0

Conwaylife(康威生命游戏)

Conway's Game of Life is a two-dimensional cellular automaton.

The "game" is played on a two-dimensional grid of cells, where each cell is either 1 (alive) or 0 (dead). At each time step, each cell changes state depending on how many neighbours it has:

0-1 neighbour: Cell becomes 0.
2 neighbours: Cell state does not change.
3 neighbours: Cell becomes 1.
4+ neighbours: Cell becomes 0.

The game is formulated for an infinite grid. In this circuit, we will use a 16x16 grid. To make things more interesting, we will use a 16x16 toroid, where the sides wrap around to the other side of the grid. For example, the corner cell (0,0) has 8 neighbours: (15,1), (15,0), (15,15), (0,1), (0,15), (1,1), (1,0), and (1,15). The 16x16 grid is represented by a length 256 vector, where each row of 16 cells is represented by a sub-vector: q[15:0] is row 0, q[31:16] is row 1, etc. (This tool accepts SystemVerilog, so you may use 2D vectors if you wish.)

load: Loads data into q at the next clock edge, for loading initial state.
q: The 16x16 current state of the game, updated every clock cycle.

The game state should advance by one timestep every clock cycle.

John Conway, mathematician and creator of the Game of Life cellular automaton, passed away from COVID-19 on April 11, 2020.

简单介绍就是存在一个16*16的方格，其中每个单元格的状态只有0和1两种状态且取决于其相邻格内的单元格状态，条件如下：

相邻格内有0-1个1：该单元格状态置0

相邻格内有2个1：该单元格状态保持不变

相邻格内有3个1：该单元格状态置1

相邻格内有4+个1：该单元格状态置0

16*16单元格如下，需要特别注意左上、右上、左下、右下、左列、上列、右列、下列八种情况下的单元格

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output [255:0] q ); 
    reg [3:0] sum;//计相邻单元格内1的数量
    integer i;
    
    always @(posedge clk) begin
        if(load)
            q<=data;
        else begin
            for(i=0;i<256;i=i+1) begin
            if(i==0)//左上
                sum=q[1]+q[15]+q[16]+q[17]+q[31]+q[240]+q[241]+q[255];
        	else if(i==15)//右上
                sum=q[0]+q[14]+q[16]+q[30]+q[31]+q[240]+q[254]+q[255];
        	else if(i==240)//左下
                sum=q[0]+q[1]+q[15]+q[224]+q[225]+q[239]+q[241]+q[255];
        	else if(i==255)//右下
                sum=q[0]+q[14]+q[15]+q[224]+q[238]+q[239]+q[240]+q[254];
        	else if(0<i&i<15)//上列
            	sum=q[i-1]+q[i+1]+q[i+15]+q[i+16]+q[i+17]+q[i+239]+q[i+240]+q[i+241];
        	else if(240<i&i<255)//下列
                sum=q[i-241]+q[i-240]+q[i-239]+q[i-1]+q[i+1]+q[i-17]+q[i-16]+q[i-15];
                else if(i%16==0 && i<240 && i>0)//左列
                sum=q[i-16]+q[i-15]+q[i-1]+q[i+1]+q[i+31]+q[i+15]+q[i+16]+q[i+17];
                else if(i%16==15 && i<255 && i>15)//右列
                sum=q[i-31]+q[i-15]+q[i-16]+q[i-17]+q[i-1]+q[i+1]+q[i+16]+q[i+15];
        	else
                sum=q[i-15]+q[i-16]+q[i-17]+q[i-1]+q[i+1]+q[i+15]+q[i+16]+q[i+17];
        
        	case(sum)
                4'd2:q[i]<=q[i];
                4'd3:q[i]<=1;
                default:q[i]<=0;
            endcase
            end
    	end
    end
endmodule