verilog语言编写4-16译码器@liuchao_L
4-16译码器verilog源文件
module my4_16(
a,
b,
c,
d,
out
);
input a;
input b;
input c;
input d;
output reg[15:0]out;
always@(a,b,c,d)begin
case({a,b,c,d})
4'b0000:out = 16'b0000_0000_0000_0001;
4'b0001:out = 16'b0000_0000_0000_0010;
4'b0010:out = 16'b0000_0000_0000_0100;
4'b0011:out = 16'b0000_0000_0000_1000;
4'b0100:out = 16'b0000_0000_0001_0000;
4'b0101:out = 16'b0000_0000_0010_0000;
4'b0110:out = 16'b0000_0000_0100_0000;
4'b0111:out = 16'b0000_0000_1000_0000;
4'b1000:out = 16'b0000_0001_0000_0000;
4'b1001:out = 16'b0000_0010_0000_0000;
4'b1010:out = 16'b0000