2021-08-16

HDLbits

Consider the state machine shown below, which has one input w and one output z.
Assume that you wish to implement the FSM using three flip-flops and state codes y[3:1] = 000, 001, … , 101 for states A, B, … , F, respectively. Show a state-assigned table for this FSM. Derive a next-state expression for the flip-flop y[2].
Implement just the next-state logic for y[2]. (This is much more a FSM question than a Verilog coding question. Oh well.)
这个题的大概意思就是，有下图这样一个状态机，然后让你写y[2]的次态表达式。

下面展示一些 内联代码片。

module top_module (
    input [3:1] y,
    input w,
    output Y2);
    assign Y2 = (y==3'b001)||(y==3'b101)||(y==3'b010&&w==1)||(y==3'b100&&w==1);

endmodule