单bit信号由快到慢跨时钟域（Verilog）

代码：

module signal_clock(
	input clk_a,
	input rst_n_a,
	input signal_a,
	input clk_b,
	input rst_n_b,
	output signal_b
);
	reg state_a;
	reg state_b1;
	reg state_b2;
	reg state_b3;
	
	//将signal_a脉冲信号转化为沿信号
	always@(posedge clk_a or negedge rst_n_a)begin
		if(!rst_n_a)
			state_a <= 1'b0;
		else if(signal_a)
			state_a <= ~state_a;
		else
			state_a <= state_a;
	end
	
	//将沿信号同步到时钟域b
	always@(posedge clk_b or negedge rst_n_b)begin
		if(!rst_n_b)begin
			state_b1 <= 1'b0;
			state_b2 <= 1'b0;
			state_b3 <= 1'b0;
		end
		else begin
			state_b1 <= state_a;
			state_b2 <= state_b1;
			state_b3 <= state_b2;
		end 
	end

	//signal_b
	assign signal_b = state_b2 ^ state_b3;

endmodule

RTL视图：