【Verilog】语法基础练习

 

Norgate - HDLBits (01xz.net)

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=!(a||b);
endmodule

Wire decl - HDLBits (01xz.net)

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
	
    wire or_in_ab,or_in_cd;
    assign or_in_ab=a&b;
    assign or_in_cd=c&d;
    assign out=or_in_ab||or_in_cd;
    assign out_n=!out;
endmodule

7458 - HDLBits (01xz.net) 

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
	
	wire and_p2ab,and_p1abc,and_p1def,and_p2cd;
    
    assign and_p2ab=p2a&&p2b;
    assign and_p2cd=p2c&&p2d;
    
    assign and_p1abc=p1a&&p1b&&p1c;
    assign and_p1def=p1d&&p1e&&p1f;
    
    assign p2y=and_p2cd||and_p2ab;
    assign p1y=and_p1def||and_p1abc;
endmodule

https://hdlbits.01xz.net/wiki/Vector0

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration
	
    assign o0=vec[0];
    assign o1=vec[1];
    assign o2=vec[2];
    
    assign outv=vec;
    
endmodule

https://hdlbits.01xz.net/wiki/Vector1

A Bit of Practice

Build a combinational circuit that splits an input half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes.

`default_nettype none     // Disable implicit nets. Reduces some types of bugs.
module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );

    assign out_hi=in[15:8];
    assign out_lo=in[7:0];
    
endmodule

https://hdlbits.01xz.net/wiki/Vector2

module top_module( 
    input [31:0] in,
    output [31:0] out );//

    // assign out[31:24] = ...;
    assign out[31:24]=in[7:0];
    assign out[23:16]=in[15:8];
    assign out[15:8]=in[23:16];
    assign out[7:0]=in[31:24];
endmodule

https://hdlbits.01xz.net/wiki/Vectorgates

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);

    assign out_or_bitwise=a|b;
    assign out_or_logical=a||b;
    assign out_not[2:0]=~a;
    assign out_not[5:3]=~b;
    
endmodule

https://hdlbits.01xz.net/wiki/Gates4

Build a combinational circuit with four inputs, in[3:0].

There are 3 outputs:

• out_and: output of a 4-input AND gate.
• out_or: output of a 4-input OR gate.
• out_xor: output of a 4-input XOR gate.

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);

    assign out_and=in[3]&&in[2]&&in[1]&&in[0];
    assign out_or=in[3]||in[2]||in[1]||in[0];
    assign out_xor=in[3]^in[2]^in[1]^in[0];
endmodule

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);

    assign out_and=∈
    assign out_or=|in;
    assign out_xor=^in;
endmodule

https://hdlbits.01xz.net/wiki/Vector3

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//

    // assign { ... } = { ... };

    assign {w,x,y,z}={a,b,c,d,e,f,2'b11};
endmodule

https://hdlbits.01xz.net/wiki/Vector4

module top_module (
    input [7:0] in,
    output [31:0] out );//

    // assign out = { replicate-sign-bit , the-input };
    assign out={{24{in[7]}},in};
endmodule

https://hdlbits.01xz.net/wiki/Vector5

Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal.

out[24] = ~a ^ a;   // a == a, so out[24] is always 1.
out[23] = ~a ^ b;
out[22] = ~a ^ c;
...
out[ 1] = ~e ^ d;
out[ 0] = ~e ^ e;

module top_module (
    input a, b, c, d, e,
    output [24:0] out );//

    // The output is XNOR of two vectors created by 
    // concatenating and replicating the five inputs.
    // assign out = ~{ ... } ^ { ... };
    assign out=~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}}^{{5{a,b,c,d,e}}};
endmodule

https://hdlbits.01xz.net/wiki/Module

module top_module ( input a, input b, output out );

    mod_a mod_a1 ( a, b, out );
    
endmodule

 

module top_module ( input a, input b, output out );

    mod_a mod_a1(.out(out),.in1(a),.in2(b));
    
endmodule

https://hdlbits.01xz.net/wiki/Module_pos

This problem is similar to the previous one (module). You are given a module named mod_a that has 2 outputs and 4 inputs, in that order. You must connect the 6 ports by position to your top-level module's ports out1, out2, a, b, c, and d, in that order.

You are given the following module:

module mod_a ( output, output, input, input, input, input );

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a mod_a1(out1,out2,a,b,c,d);
endmodule

https://hdlbits.01xz.net/wiki/Module_name

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);

    mod_a mod_a1(.out1(out1),.out2(out2),.in1(a),.in2(b),.in3(c),.in4(d));
endmodule

https://hdlbits.01xz.net/wiki/Module_shift8

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);

    wire[7:0] out1,out2,out3;
    my_dff8 my_dff8_1(.clk(clk),.d(d),.q(out1));
    my_dff8 my_dff8_2(.clk(clk),.d(out1),.q(out2));
    my_dff8 my_dff8_3(.clk(clk),.d(out2),.q(out3));
    
    always @(*)begin
        case (sel)
            2'b00:q=d;
            2'b01:q=out1;
            2'b10:q=out2;
            2'b11:q=out3;
        endcase
    end
endmodule