山南水北有一方的博客

1.verilog中比较大小只能用a>b和a<b,满足则表达式逻辑为1，反之为0。不能用（a-b），因为结果不管是正数还是负数，逻辑都判为1.

1.判断相等可以判断多位```bashmodule top_module ( input [1:0] A, input [1:0] B, output z ); assign z=(A==B);endmodule

1.BCD码进位时，判断条件是 if(m < 8’h59)，这里是用16进制数表示，即4位二进制数表示5，四位二进制数表示9，BCD数实际上就是十六进制数，不过是认为设置满10进1.自己写的：module top_module( input clk, input reset, input ena, output pm, output [7:0] hh, output [7:0] mm, output [7:0] ss); .

问题1：一位全加器assign sum = a ^ b ^ cin;assign cout = a&b | a&cin | b&cin;一位全加器，sum为输入加进位位异或（即1的个数为奇数时，sum==1);cout为a&b&cin;即三个输入是1时为1，上面代码里写法是为了保证输入延迟一样。不过现在FPGA基本是四输入查找表，所以直接a&amp...

这个题是检测下降沿，检测到后out一直为高，知道reset == 1时，out为0。我自己做：先通过边沿检测，得到一个脉冲信号，然后if这个脉冲信号为高，将其输出给out,输出为低就不管（会保持前面状态）。但是这样做，边沿检测时会延迟一个clk，在将其输出给out时又会延迟一个clk,这样就与题目中给的时序图不符，看网上答案：module top_module ( input clk, input reset, input [31:0] in, output [31:.

1.关于例化程序段执行顺序的问题 generate for(i=1;i<=100;i=i+1) begin : gen bcd_fadd qq ( .a(a[(i*4-4)+:4]), .b(b[(i*4-4)+:4]), ...

module top_module( input [2:0] a, b, input cin, output [2:0] cout, output [2:0] sum ); task add; input a,b,c; output co,s; begin co = a&b|a&c|b&c; s=a^b^c; end endtask a.

BCD码（Binary-Coded Decimal‎），用4位二进制数来表示1位十进制数中的0~9这10个数码，是一种二进制的数字编码形式。module top_module ( input clk, input reset, output OneHertz, output [2:0] c_enable); // wire [3:0] q1,q2,q3; assign c_enable[0] = 1'b1; assign c_enable[1] .

module top_module ( input clk, input w, R, E, L, output Q); wire a,d; assign a = E ? w : Q; assign d = L ? R : a; always@(posedge clk) begin Q <= d; endendmodulea、d的产生用组合逻辑。

module top_module( input clk, input reset, // Active-high synchronous reset to 32'h1 output [31:0] q); always@(posedge clk) begin if(reset) q <= 32'b1; else begin q[31] <= q[0]; .

1.加法中，数据溢出的情况只有两种，两证正数相加结果却为负数，两负数相加，结果却为正数。2.注意区分 逻辑或| 和 +逻辑判断时要用|assign overflow = （a[7]&b[7]&!s[7]）|（!a[7]&!b[7]&s[7]）;assign overflow = a[7]&b[7]&!s[7] + !a[7]&!b[7]&s[7];，其次对于基本运算符的优先级问题：常用的： ！ & ^ | &&

问题1.if一般结构，不需要endifalways @(*) begin if (condition) begin out = x; end else begin out = y; endend问题2.case一般结构，需要endcasealways @(*) begin // This is a combinati...

module aa(output [2:0] a,output [2:0] c);//wire [2:0] a, c; // Two vectorsassign a = 3'b101; // a = 101assign b = a; // b = 1 implicitly-created wireassign c = b; // c = 001 &lt...

1.向量下标可以是个wire类型的变量Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. In particular, selecting one bit out of a vector us...

问题点就是dfr的确定。第一感觉dfr是导函数，所以先定义一个延迟信号s_reg。然后原题中是previous>current时，dfr <=1。延迟信号s_reg是原信号的延迟，所以是在同一个clk下的s前一时刻值。所以求导的话应该是s - s_reg;而不是s_reg - s.所以原题中意思=》 if (s_reg > s) dfr <= 1’b1;故这一段应该是always@(posedge clk) beginif (reset) dfr <= 1.

The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4’b0001, B=4’b0010, C=4’b0100, D=4’b1000.状态转移。什么时候next_state是A呢？从表中可以很容易看出，当前state=A&in=0时

1.Rule 90Rule 90 is a one-dimensional cellular automaton with interesting properties.The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell’s two current neighbou

第115题 Exams/ece241 2013 q12In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is “random access”, as in a typical RAM. You will then use the circuit to realize a 3