HDLBits Day14 83数据选择器

第115题 Exams/ece241 2013 q12

In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is “random access”, as in a typical RAM. You will then use the circuit to realize a 3-input logic function.

First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]…Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input controls whether to shift. Then, extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit’s behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).

Module Declaration
module top_module (
input clk,
input enable,
input S,
input A, B, C,
output Z );

my answer:

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    reg [7:0] Q;
    always@(posedge clk)
        if(enable) 
            Q[7:0] <= {Q[6:0], S};

    always@(*)
        case({A,B,C})
            3'b000:Z = Q[0];
            3'b001:Z = Q[1];
            3'b010:Z = Q[2];
            3'b011:Z = Q[3];
            3'b100:Z = Q[4];
            3'b101:Z = Q[5];
            3'b110:Z = Q[6];
            3'b111:Z = Q[7];
        endcase
    
       
endmodule

出现的问题：
1.组合逻辑还是时序逻辑
数据必须在clk驱动下，存入Q。虽然assign Q[7:0] = enable ? {Q[6:0], S} : Q[7:0] ;不报错，但是形成锁存器，不能这样写。
后面数据选择时，应采用组合逻辑，在always@(*)中使用case语句。
2.写数据时不管任何情况，应写上位宽，防止出现奇怪错误。比如，没定义位宽，它默认十进制数，容易忘了。