Rule90

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    
    reg [511:0] q_last;
  
    always @(posedge clk)
        begin
            if(load)
                q <= data;
            else
                q <= q_last;
         end
    //组合逻辑构建下一个q
    genvar i;
    generate
        for(i=0; i<=511; i++)
            begin: my_block_name
                if(i==0)
                    assign q_last[i] = q[1]^0;
                else
                    if(i == 511)
                        assign q_last[511] = q[510]^0;
                	else
                        assign q_last[i] = q[i+1]^q[i-1];
            end
    endgenerate
                
endmodule

看了下参考答案，自己做的比较复杂，没有运用vecto思想；在此贴上官方的参考答案

module top_module(
	input clk,
	input load,
	input [511:0] data,
	output reg [511:0] q);
	
	always @(posedge clk) begin
		if (load)
			q <= data;	// Load the DFFs with a value.
		else begin
			// At each clock, the DFF storing each bit position becomes the XOR of its left neighbour
			// and its right neighbour. Since the operation is the same for every
			// bit position, it can be written as a single operation on vectors.
			// The shifts are accomplished using part select and concatenation operators.
			
			//     left           right
			//  neighbour       neighbour
			q <= q[511:1] ^ {q[510:0], 1'b0} ;
		end
	end
endmodule