Rule90\Rule110_HDLbits

 

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    reg [8:0] i;
  
    always @(posedge clk)
        begin
            if(load) q<=data;
 			else 
                begin q[0]<=q[1]^0;q[511]<=q[510]^0;
           		for(i=1;i<=510;i++) q[i]<=q[i-1]^q[i+1];
                end              
        end
endmodule

 

写出卡诺图化简得到的变化关系

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
    reg [8:0] i;
  
    always @(posedge clk)
        begin
            if(load) q<=data;
 			else 
                begin q[0]<=(0&~q[0])|(q[0]&1)|(~q[1]&0);
                      q[511]<=(q[510]&~q[511])|(q[511]&~q[510])|(1&q[510]);
                      for(i=1;i<=510;i++) 
                      q[i]<=(q[i-1]&~q[i])|(q[i]&~q[i-1])|(~q[i+1]&q[i-1]);
                end              
        end
    
endmodule