题目描述
This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
This exercise is the same as fsm2, but using synchronous reset.
代码
module top_module(
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
OFF: if(j==1)
next_state<=ON;
else if(j==0)
next_state<=OFF;
ON: if(k==1)
next_state<=OFF;
else if(k==0)
next_state<=ON;
endcase
end
always @(posedge clk) begin
// State flip-flops with synchronous reset
if(reset)
state<=OFF;
else
state<=next_state;
end
// Output logic
// assign out = (state == ...);
assign out = state;
endmodule