V语言 FSM题目

一个FSM实例

module test4( 
    input clk,
    input reset,      
    input data,
    output reg [3:0] count,
    output reg counting,
    output reg done,
    input ack 
);

reg [4:0] state,next_state;
reg [3:0] temp,timer;

always @(posedge clk) begin
    if(reset)begin
        state<=5'b0;
        next_state<=5'b0;
        count<=4'b0;
        counting<=1'b0;
        done<=1'b0;
        temp=4'b0;
    end 
    else begin
        state=next_state;
    end
    case (state)
        0: begin
            temp={temp[2:0],data};
            if(temp==4'b1101)begin
                next_state=1;
                timer=4'b0;
            end
        end
        1,2,3: begin 
            timer<={timer[2:0],data};
            next_state=state+1;
        end
        4:begin
            timer={timer[2:0],data};
            next_state=state+1;
            count<=timer;
            counting<=1'b1;
        end
        5:begin 
            if(count)begin
                count<=count-1;
            end else begin
                counting<=1'b0;
                next_state=6;
            end
        end
        6:begin
            done<=1'b1;
            if(ack) begin
                next_state<=7; 
            end
        end
        7:begin
            done<=1'b0;
            next_state=0;
        end
    endcase
end	
endmodule