Verilog 复杂设计 练习

• 设计要求

 

• 代码编写

// *********************************************************************************
// Project Name : 
// Email        : 854923411@qq.com
// Website      : 
// Author       :  
// Create Time  : 202// 
// File Name    : .v
// Module Name  : 
// Abstract     :
// editor		: sublime text 3
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 202//    jianqiao           1.0                     Original
//  
//
// *********************************************************************************
`timescale      1ns/1ps
module mul2port (
	dina,
	dinb,
	dinc,
	dind,
	sela,
	selb,
	clk,
	rstn,
	result_a,
	resutl_b
	);
  
  parameter A_W = 3,
  			B_W = 2,
  			C_W = 4,
  			D_W = 4,
  			RESULT_A = 7,
  			RESULT_B = 6;

  input	[A_W-1:0]	dina;
  input [B_W-1:0] 	dinb;
  input [C_W-1:0] 	dinc;
  input [D_W-1:0]  	dind;
  input 		sela;
  input 		selb;
  input 		clk	;
  input 		rstn;
  output [RESULT_A-1:0] 	result_a;
  output [RESULT_B-1:0] 	resutl_b;

  wire [A_W-1:0] 	dina;
  wire [B_W-1:0] 	dinb;
  wire [C_W-1:0] 	dinc;
  wire [D_W-1:0]  	dind;
  
  reg [RESULT_A-1:0]		result_a;
  reg [RESULT_B-1:0] 		resutl_b;
  wire [RESULT_A-1:0]		mul_result_7;
  wire [RESULT_B-1:0] 		mul_result_6;

//----------控制选择器的控制端------------------
  reg sel_tmp;
  always @ (posedge clk or negedge rstn) begin 
  	if (rstn == 1'b0)
  		sel_tmp <= 1'b0;
    else 
        sel_tmp <= sela && selb;
  end 

//-------------mul_4_3模块的输入端口的选择器-------
  wire [D_W-1:0]		mul_tmp;
  assign mul_tmp = sel_tmp ? dinc : dind ;

//-----------输出端口部分的寄存器---------------
  always @ (posedge clk or negedge rstn) begin 
  	if (rstn == 1'b0)
  		result_a <= 7'd0;
  	else 
  		result_a <= mul_result_7;
  end 
  always @(posedge clk or negedge rstn ) begin
  	if (rstn == 1'b0) 
  		resutl_b <= 6'd0;
  	else 
  		resutl_b <= mul_result_6;
  end

  //----------例化mul模块----------------------
  mul_mode mul_4_3 (
  	.clk	(clk),
  	.rstn	(rstn),
  	.mul_a	(dina),
  	.mul_b	(mul_tmp),
  	.mul_result (mul_result_7)
  	);

  mul_mode #(.MUL_B_SIZE(2),.MUL_RESULT_SIZE(6) ) mul_4_2(
	.clk 	(clk),
	.rstn	(rstn),
	.mul_a	(dinb),
	.mul_b 	(mul_tmp),
	.mul_result (mul_result_6)
	);

endmodule

例化模块

module mul_mode (
    clk,
    rstn,
    mul_a,
    mul_b,
    mul_result
    );

  parameter MUL_A_SIZE = 4,
            MUL_B_SIZE = 3,
            MUL_RESULT_SIZE = 7;
  input    clk;
  input    rstn;
  input[MUL_A_SIZE-1:0] mul_a;
  input[MUL_B_SIZE-1:0] mul_b;
  output[MUL_RESULT_SIZE-1:0]  mul_result;

  wire clk,rstn;
  wire [MUL_A_SIZE-1:0] mul_a;
  wire [MUL_B_SIZE-1:0] mul_b;
  reg  [MUL_RESULT_SIZE-1:0] mul_result;

 // wire [MUL_RESULT_SIZE-1:0]  s;

 // assign s = {mul_a,mul_b};
  always @ (posedge clk or negedge rstn) begin 
  if (rstn == 1'b0)
    mul_result <= 7'd0;
  else 
    mul_result <= mul_a * mul_b;
  end 

  endmodule 

 

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