Verilog刷题[hdlbits] ：Module fadd

最新推荐文章于 2024-04-20 11:43:27 发布

卡布达吃西瓜

最新推荐文章于 2024-04-20 11:43:27 发布

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分类专栏： verilog 文章标签： fpga开发 verilog hdlbits

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题目：Module fadd

In this exercise, you will create a circuit with two levels of hierarchy. Your top_module will instantiate two copies of add16 (provided), each of which will instantiate 16 copies of add1 (which you must write). Thus, you must write two modules: top_module and add1.

在本练习中，您将创建一个具有两层层次结构的电路。您的top_module将实例化add16的两个副本(已提供)，每个副本将实例化add1的16个副本(必须编写)。因此，必须编写两个模块:top_module和add1。

Like module_add, you are given a module add16 that performs a 16-bit addition. You must instantiate two of them to create a 32-bit adder. One add16 module computes the lower 16 bits of the addition result, while the second add16 module computes the upper 16 bits of the result. Your 32-bit adder does not need to handle carry-in (assume 0) or carry-out (ignored).

与module_add一样，您将获得一个执行16位加法的模块add16。要创建一个32位加法器，必须实例化其中的两个。一个add16模块计算加法结果的下16位，而第二个add16模块计算结果的上16位。您的32位加法器不需要处理低位向本位的进位输入信号(假设为0)或本位向高位的进位输出信号(忽略)。

Connect the add16 modules together as shown in the diagram below. The provided module add16 has the following declaration:

将add16模块连接在一起，如下图所示。所提供的模块add16有以下声明:
module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

Within each add16, 16 full adders (module add1, not provided) are instantiated to actually perform the addition. You must write the full adder module that has the following declaration:

在每个add16中，将实例化16个完整加法器(模块add1，未提供)以实际执行加法。你必须编写完整的加法器模块，该模块具有以下声明:

module add1 ( input a, input b, input cin, output sum, output cout );

模块add1(输入a，输入b，输入cin，输出sum，输出cout);

Recall that a full adder computes the sum and carry-out of a+b+cin.

回忆一下，全加法器计算a+b+cin的和和。

In summary, there are three modules in this design:

综上所述，本次设计主要分为三个模块:

top_module — Your top-level module that contains two of…
add16, provided — A 16-bit adder module that is composed of 16 of…
add1 — A 1-bit full adder module.

top_module -你的顶级模块，包含两个…
一个16位加法器模块，由16个…
add1 - 1位全加法器模块。

If your submission is missing a module add1, you will get an error message that says Error (12006): Node instance “user_fadd[0].a1” instantiates undefined entity “add1”.

如果您的提交缺少模块add1，您将得到一条错误消息:error (2006): Node instance "user_fadd[0]。A1”实例化未定义实体“add1”。

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire cout;
	add16 add16_init_0( 
        .a(a[15:0]), 
        .b(b[15:0]),
        .cin(0), 
        .sum(sum[15:0]), 
        .cout(cout) 
    );
	add16 add16_init_1( 
        .a(a[31:16]), 
        .b(b[31:16]),
        .cin(cout), 
        .sum(sum[31:16]), 
        .cout() 
    );  

endmodule
    
module add1
(
	input a,     	//加数
	input b,		//加数
	input cin,		//进位
	output sum,		//结果
	output cout		//进位
);
	assign sum = a^b^cin;
	assign cout = (a&b)|((a^b)&cin);
endmodule