在数字芯片设计中,存在始终mux时,需要做glitch free处理,下面为某厂的clk_mux glitch free原代码,仅供参考
module DWC_clkrst_sfsm ( // ---- inputs --------------- input auxclk, // Free running auxiliary clock input, this clock is always available, including low power states input auxclk_sel, // auxclk is selected to drive aux_clk, generated by the PM state machine, synchronous to aux_clk input coreclk, // core clock, prior to the clock gating logic implemented in this module input aux_sync_pwr_rst_n, // power on reset synchronously de-asserted with auxclk input pclk_sync_pwr_rst_n, // power on reset synchronously de-asserted with pclk // ---- outputs --------------- output aux_clk, // switched auxiliary clock used by the core output aux_clk_active, // auxclk is actively driving aux_clk output core_clk_active ); parameter TP = `TP; // ======== start of glitch free aux_clk mux / core_clk gate ==