【verilog学习13】HDLBits：More Verilog Features (for 循环)

I. Conditional (conditional ternary operater)

1.代码编写

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//
    wire [7:0] min2,min3;
    // assign intermediate_result1 = compare? true: false;
    assign min2=(a<b)?a:b;
    assign min3=(c<d)?c:d;
    assign min=(min2<min3)?min2:min3;
endmodule

2.提交结果

success

3.题目分析

介绍了Verilog中的ternary operator三元运算符，类似于C语言中的if_else语句。

Verilog has a ternary conditional operator ( ? : ) much like C:
(condition ? if_true : if_false)

II. Reduction (Reduction operaters)

1.代码编写

module top_module (
    input [7:0] in,
    output parity); 
    assign parity = ^in[7:0];
endmodule

2.提交结果

3.题目分析

• 这里介绍了一种缩简运算符，可避免逐位运算时那些乏味的（tedious）操作。
  The reduction operators can do AND, OR, and XOR of the bits of a vector, producing one bit of output:
  & a[3:0] // AND: a[3]&a[2]&a[1]&a[0]. Equivalent to (a[3:0] == 4’hf)
  | b[3:0] //OR: b[3]|b[2]|b[1]|b[0]. Equivalent to (b[3:0] != 4’h0)
  ^ c[2:0] // XOR: c[2] ^ c[1] ^ c[0]

• These are unary operators that have only one operand (similar to the NOT operators ! and ~).
  You can also invert the outputs of these to create NAND, NOR, and XNOR gates, e.g., (~& d[7:0]).

• 题目要求进行parity checking(奇偶校验)，及将in的各位进行XOR。

III. Gates100 (Reduction: even wider gates)

1.代码编写

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
	assign out_and=& in;
    assign out_or=| in;
    assign out_xor=^ in;
endmodule

2.提交结果

3.题目分析

Build a combinational circuit with 100 inputs, in[99:0].

There are 3 outputs:

• out_and: output of a 100-input AND gate.
• out_or: output of a 100-input OR gate.
• out_xor: output of a 100-input XOR gate.

IV. Vector100r (combinational for-loop:Vector reversal2)

1.代码编写

//===============================方法1：=============================
module top_module( 
    input [99:0] in,
    output [99:0] out
);
    integer i;
    always@(*) begin
        for(i=0;i<100;i++) begin
            out[99-i]=in[i];
        end
    end
endmodule

//===============================方法2：=============================
module top_module( 
    input [99:0] in,
    output [99:0] out
);
    generate
        genvar i;
        for(i=0;i<100;i++) begin:reverse
            assign out[99-i]=in[i];
        end
    endgenerate
endmodule

2.提交结果

3.题目分析

generate_for
当verilog中进行重复操作时，常常用到generate_for语句。

• 用generate_endgenerate指定范围，其中可包括过程块、连续赋值语句等等。

对于generate_for:

• 必须通过genvar关键字定义变量。
• 在for后一定加begin_end，即使只有一句。
• for语句必须有名字(begin:filename)，否则报错：

this block requires a name File:

always_for

• I would prefer a combinational always block in this case because module instantiations (which require generate blocks) aren’t needed.
• 而generate需要实例化，filename用作generate循环的实例名称（filename[0]、filename[1]……filename[n]）。

V.Popcount255 (combinational for-loop:255-bit population count)

1.代码编写

module top_module( 
    input [254:0] in,
    output [7:0] out );
    integer i;
    always@(*) begin
        out=8'd0;
        for(i=0;i<255;i++)
            out=(in[i])?out+8'd1:out;
    end
endmodule

2.提交结果

3.题目分析

So many things to add… How about a for loop?

VI.Adder100i (Generate for-loop: 100-bit binary adder 2)

1.代码编写

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    assign {cout[0],sum[0]}=a[0]+b[0]+cin;
	generate 
        genvar i;
        for(i=1;i<100;i++)begin:Fadder
            assign {cout[i],sum[i]}=a[i]+b[i]+cout[i-1];
        end
    endgenerate
endmodule

2.提交结果

3.题目分析

设计100bits加法器，由于需要非常多的全加器，所以引入for循环。

VII.Bcdadd100(Generate for-loop: 100-digit BCD Adder)

1.代码编写

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    wire [99:0] cout2;
	generate
        genvar i;
        for(i=0;i<100;i=i+1) begin: BCDAdder
            if(!i)begin //i=0初位
                bcd_fadd instance1(.a(a[(i+1)*4-1:i*4]),.b(b[(i+1)*4-1:i*4]),.cin(cin),.cout(cout2[i]),.sum(sum[(i+1)*4-1:i*4]));
            end
            else bcd_fadd instance2(.a(a[(i+1)*4-1:i*4]),.b(b[(i+1)*4-1:i*4]),.cin(cout2[i-1]),.cout(cout2[i]),.sum(sum[(i+1)*4-1:i*4]));
        end
        assign cout=cout2[99];
    endgenerate
endmodule

2.提交结果

3.题目分析

实例化，注意好循环变量与Vector项数对应的关系即可。
如果简单地用a[i+3:i]、b[i+3:i]的话，可能需要一个cout[399:0]，i也是取0 ~ 399；但里这用a[(i+1)* 4-1:i *4]、b[(i+1) *4-1:i *4]，只需要一个cout[99:0]，i取0 ~ 99即可。