数字IC验证学习笔记_AHB总线

数字IC验证学习笔记

AHB总线

1.  AHB总线测试用例（TestCase）
2.  AHB总线测试平台（TestBench）

1. AHB总线测试用例（TestCase）

1.1 写操作

• Verilog代码

task ahb_write(input [31:0] addr, input [31:0] wdata);
begins
	@(posedge hclk);
	#1;
	hsize = 2'b10;
	htrans = NONSEQ;
	hwrite = 1;
	hsel = 1;
	hready = 1;
	haddr = addr;
	@(posedge hclk);
	#1;
	hsize = 2'b00;
	htrans = IDLE;
	hwrite = 0;
	hsel = 0;
	hwdata = wdata;
	@(posedge hclk);
	#1;
	Haddr = 32'h0;
	@(posedge hclk);
end
endtask

1.2 读操作

task ahb_read(input [31:0] addr, output [31:0] rdata);
begin
  @(posedge hclk);
  #1; //
  haddr =  addr;
  hsize = 2'b10;
  htrans = NONSEQ;
  hwrite = 0;
  hsel = 1;
  @(posedge hclk);
  #1;
  hsize = 2'b00;
  htrans = IDLE;
  hwrite = 0;
  hsel = 0;
  @(posedge hclk);
  #1;
  rdata = hrdata;
  haddr = 32'b0;
  @(posedge hclk);
  
  
end
endtask

//*****************************
//     testcase.sv
//*****************************
ahb_if.ahb_write(32'h04, 32'h01);
#10;
ahb_if.ahb_read(32'h08,rdata);

2. AHB总线测试平台（TestBench）

• System Verilog interface

//*****************************
//       interface
//*****************************
interface ahb_if();
logic hclk;
logic hresetn;
logic hsel;
logic hwrite;
logic hready;
logic [2:0] size;
logic [2:0] hburst;
logic [1:0] htrans;
logic [31:0] hwdata;
logic [31:0] haddr;
 
logic hready_resp;
logic [1:0] hresp;
logic [31:0] hrdata;
 
reg [31:0] rdata;
//*************
//clock generator
//*************
initial beign
hclk = 0;
Forever begin
#10 hclk = ~hclk; 
end
 
end
parameter IDLe = 2'b00,
bUSY = 2'b01,
NONSeQ = 2'b10,
SeQ = 2'b11;
 
initial begin
hresetn = 0;
htrans = 0;
hsize = 3'b0;
hburst = 3'b0;
hwrite = 0;
hsel -= 0;
hready = 0;
haddr = 0;
#200;
hresetn = 1;
 
`include "tesetcase.v"
 
#100;
$finish;
 
 
end
 
task ahb_write(input [31:0] addr, input [31:0] wdata);
begins
@(posedge hclk);
#1;
hsize = 2'b10;
htrans = NONSeQ;
hwrite = 1;
hsel = 1;
hready = 1;
haddr = addr;
@(posedge hclk);
#1;
hsize = 2'b00;
htrans = IDLe;
hwrite = 0;
hsel = 0;
hwdata = wdata;
@(posedge hclk);
#1;
haddr = 32'h0;
@(posedge hclk);
end
endtask
 
task ahb_read(input [31:0] addr, output [31:0] rdata);
begin
@(posedge hclk);
#1; //
haddr =  addr;
hsize = 2'b10;
htrans = NONSeQ;
hwrite = 0;
hsel = 1;
@(posedge hclk);
#1;
hsize = 2'b00;
htrans = IDLe;
hwrite = 0;
hsel = 0;
@(posedge hclk);
#1;
rdata = hrdata;
haddr = 32'b0;
@(posedge hclk);
 
 
end
endtask
endinterface

• System Verilog Testbench

module ahb_top_tb
ahb_if top_ahb_if();
reg [31:0] rdata;
 
logic [15:0] a;
logic [15:0] b;
//*************
//dump waveform
//*************
`ifdefine Sim
initial begin
        $fsdbDumpfile("verilog.fsdb");
        $fsdbDumpvars(1,ahb_test_tb);
        $fsdbDumpSVa;
 
end
endif
 
initial begin 
#1000;
`include "testcase.sv"
#100;
$finish;
end
 
ahb_top u_ahb_top(
.hclk (ahb_if.hclk);
.hresetn (ahb_if.hresetn);
 
);
endmodule

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【注】：个人学习笔记，如有错误，望不吝赐教，这厢有礼了~~~

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