2.1 Basics

1、Getting Started

1.1、Getting Started

module top_module( output one );
    assign one = 1'b1;   
endmodule

1.2、Output Zero

module top_module( output zero );
    assign zero = 1'b0;      
endmodule

2、Verilog Language

2.1、Basics

2.1.1、Simple Wire

module top_module( input in, output out );
	int a;
    assign out=in;
endmodule

2.1.2、four wires

module top_module( 
    input a,b,c,
    output w,x,y,z );
	assign w=a;
    assign x=b;
    assign y=b;
    assign z=c;
endmodule

2.1.3、Invert

module top_module( input in, output out );
	assign out=!in;     // out=~in;
endmodule

2.1.4、AND Gate

module top_module( 
    input a, 
    input b, 
    output out );
	assign out=a&b;     //out=a&&b;
endmodule

2.1.5、NOR Gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=!(a|b);
endmodule

2.1.6、Xnor gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=!(a^b);
endmodule

2.1.7、Declaring wires 

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
	wire e,f,g;
    assign e=a&b;
    assign f=c&d;
    assign g=e|f;
    assign out=g;
    assign out_n=!g;
endmodule

2.1.8、7458 Chip

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    assign p1y = (p1a & p1b & p1c) | (p1f & p1e & p1d);
    assign p2y = (p2a & p2b) | (p2c & p2d);
endmodule