在数字电路中,使用 Verilog 生成不同频率的时钟和占空比是较为常见的一种设计,主要分为偶数分频,奇数分频,也可以任意进行分频和占空比的配置;(以下皆为占空比50%)
这次我分享的是由clk触发分频信号 和 由使能信号触发分频信号的两种方法
1.100MHz分出50Hz的verilog代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2023/03/03 15:25:26
// Design Name:
// Module Name: test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module tese_all(
input clk,
input rst,
output reg cnt
);
reg[27:0] tmp;
always @ (posedge clk or negedge rst)
begin
if(!rst)begin
tmp <= 0;
cnt <= 0;
end
else if(tmp == 28'd499999)
begin
tmp <= 28'd0;
cnt <= ~cnt;
end
else
tmp <= tmp + 1'b1;
end
endmodule
仿真测试图像如下可见:
![](https://img-blog.csdnimg.cn/img_convert/d1c8585732e8399d049dd105c23e0a44.png)
2.由PPS触发的分频信号verilog代码
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2023/03/03 15:25:26
// Design Name:
// Module Name: tese_all
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module tese_all(
input clk,
input rst,
input i_gps_pps,
output Yfreq,
output Nfreq1,
output Nfreq2
);
/Trigger generation/
reg pps_flag;
reg[15:0] time_cnt;
reg led_reg;
reg i_gps_pps_1;
reg gps_pps_flag;
always@(posedge clk or negedge rst)
begin
if(!rst)
i_gps_pps_1 <= 0;
else if(i_gps_pps)begin
i_gps_pps_1 <= i_gps_pps;
end
else
i_gps_pps_1 <= 0;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
pps_flag <= 0;
else if (!i_gps_pps_1 && i_gps_pps)
pps_flag <= 1;
else
pps_flag <= 0;
end
always@(posedge clk or negedge rst)
begin
if(!rst)
gps_pps_flag <= 0;
else if (!i_gps_pps_1 && i_gps_pps)
gps_pps_flag <= 1;
else
gps_pps_flag <= gps_pps_flag;
end
/*------ Trigger generation-----------------*/
always @ (posedge clk or negedge rst)
begin
if(!rst)
time_cnt<=0;
else if (gps_pps_flag)begin
if (pps_flag == 'b0)
begin
if (time_cnt =='d5000)
time_cnt<=0;
else
time_cnt<=time_cnt+1'b1;
end
else if (pps_flag == 'b1)
time_cnt<=0;
end
end
always @ (posedge clk or negedge rst)
begin
if(!rst)
led_reg<=0;
else if(time_cnt=='d5000)
led_reg<=~led_reg;
else
led_reg<=led_reg;
end
assign Yfreq = led_reg;
endmodule
仿真测试图像如下所示:
![](https://img-blog.csdnimg.cn/img_convert/3f925d703d50ce9f40035307ebf20a48.png)
注意!!!每天一个小知识: 1PPS:秒脉冲;英文全称:Pulse Per Second ;PPS(one pulse per second)信号是GPS北斗时钟服务器向用户提供的时间基准信号,一秒钟一个脉冲。1PPS信号的主要指标包括上升沿宽度、下降沿宽度、脉冲宽度、脉冲幅度。时钟模块上的GPS接收机负责接收GPS天线传输的射频信号,然后进行变频解调等信号处理,向基站提供1pps信号,进行同步。 GPS使用原子钟(原子钟,是一种计时装置,精度可以达到每2000万年才误差1秒)
这次的分享到这里over了,备忘录+1,希望看到这篇的朋友们少吃盐多运动多吃芹菜哈哈哈哈哈哈哈!