library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xunhuan6 is
port(clock,enable:in std_logic;
q:out std_logic_vector(2 downto 0);
cout:out std_logic);
end xunhuan6;
architecture one of xunhuan6 is
begin
process(clock)
variable count:std_logic_vector(2 downto 0);
begin
if clock'event and clock='1' then
if enable='1' then
if count<5 then count:=count+1;
else count:="000";
end if;
end if;
end if;
if(count=5) and ( enable='1') then cout<='1';
else cout<='0';
end if;
case count is
when "000"=> q<="000";
when "001"=> q<="001";
when "010"=> q<="011";
when "011"=> q<="111";
when "100"=> q<="101";
when "101"=> q<="100";
when others => null;
end case;
end process;
end one;