Quartus 实现全减器

期末裸考系列之例化语句实现全减器

全加器有两个半减器以及一个或门实现

1.半减器 （h_suber）

library ieee;
use ieee.std_logic_1164.all;
entity h_suber is
	port(x,y:in std_logic;
 diff,s_out:out std_logic);
end h_suber;
architecture one of h_suber is 
begin
diff <= x xor y;
s_out<=(not x)and y;
end one;

2.或门 (or2a)

library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port (a,b:in std_logic;
		  c:out std_logic);
end or2a;
architecture two of or2a is
	begin
	c<=a or b;
end two;

3.全减器实现（f_suber）

library ieee;
use ieee.std_logic_1164.all;
entity f_suber is                        --定义实体全减器
	port(x0,y0,sub_in : in std_logic;     --x0和y0为减数与被减数，subin借位输入
												
		  sub_out,diff : out std_logic);   --difer out 为本位输出，sub out为借位输出
end f_suber;
architecture three of f_suber is 
component h_suber                        --半减器例化声明


	port(x,y:in std_logic;
 diff,s_out:out std_logic);
end component;
component or2a                           --2输入或门例化声明
port (a,b:in std_logic;
		  c:out std_logic);
end component;
signal d,e,f : std_logic;                --定义敏感信号
begin 
ul:h_suber port map(x => x0,y => y0,diff=>d,s_out => e);
u2:h_suber port map(x => d, y=>sub_in,diff=>diff,s_out=>f);
u3:or2a    port map(a => f, b=>e,c=>sub_out);

end three;