pci_scan_root_bus_bridge

int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
{
    struct resource_entry *window;
    bool found = false;
    struct pci_bus *b;
    int max, bus, ret;

    if (!bridge)
        return -EINVAL;

    resource_list_for_each_entry(window, &bridge->windows)
        if (window->res->flags & IORESOURCE_BUS) {
            found = true;
            break;
        }

    ret = pci_register_host_bridge(bridge);
    if (ret < 0)
        return ret;

    b = bridge->bus;
    bus = bridge->busnr;

    if (!found) {
        dev_info(&b->dev,
         "No busn resource found for root bus, will use [bus %02x-ff]\n",
            bus);
        pci_bus_insert_busn_res(b, bus, 255);
    }

    max = pci_scan_child_bus(b);

    if (!found)
        pci_bus_update_busn_res_end(b, max);

    return 0;
}

nsigned int pci_scan_child_bus(struct pci_bus *bus)
{
    unsigned int devfn, pass, max = bus->busn_res.start;
    struct pci_dev *dev;

    dev_dbg(&bus->dev, "scanning bus\n");

    /* Go find them, Rover! */
    for (devfn = 0; devfn < 0x100; devfn += 8)
        pci_scan_slot(bus, devfn);

    /* Reserve buses for SR-IOV capability. */
    max += pci_iov_bus_range(bus);

    /*
     * After performing arch-dependent fixup of the bus, look behind
     * all PCI-to-PCI bridges on this bus.
     */
    if (!bus->is_added) {
        dev_dbg(&bus->dev, "fixups for bus\n");
        pcibios_fixup_bus(bus);
        bus->is_added = 1;
    }

    for (pass = 0; pass < 2; pass++)
        list_for_each_entry(dev, &bus->devices, bus_list) {
            if (pci_is_bridge(dev))
                max = pci_scan_bridge(bus, dev, max, pass);
        }

    /*
     * Make sure a hotplug bridge has at least the minimum requested
     * number of buses.
     */
    if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) {
        if (max - bus->busn_res.start < pci_hotplug_bus_size - 1)
            max = bus->busn_res.start + pci_hotplug_bus_size - 1;

        /* Do not allocate more buses than we have room left */
        if (max > bus->busn_res.end)
            max = bus->busn_res.end;
    }

    /*
     * We've scanned the bus and so we know all about what's on
     * the other side of any bridges that may be on this bus plus
     * any devices.
     *
     * Return how far we've got finding sub-buses.
     */
    dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
    return max;
}

/**
 * pci_scan_slot - scan a PCI slot on a bus for devices.
 * @bus: PCI bus to scan
 * @devfn: slot number to scan (must have zero function.)
 *
 * Scan a PCI slot on the specified PCI bus for devices, adding
 * discovered devices to the @bus->devices list.  New devices
 * will not have is_added set.
 *
 * Returns the number of new devices found.
 */
int pci_scan_slot(struct pci_bus *bus, int devfn)
{
    unsigned fn, nr = 0;
    struct pci_dev *dev;

    if (only_one_child(bus) && (devfn > 0))
        return 0; /* Already scanned the entire slot */

    dev = pci_scan_single_device(bus, devfn);
    if (!dev)
        return 0;
    if (!dev->is_added)
        nr++;

    for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
        dev = pci_scan_single_device(bus, devfn + fn);
        if (dev) {
            if (!dev->is_added)
                nr++;
            dev->multifunction = 1;
        }
    }

    /* only one slot has pcie device */
    if (bus->self && nr)
        pcie_aspm_init_link_state(bus->self);

    return nr;
}

struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
{
    struct pci_dev *dev;

    dev = pci_get_slot(bus, devfn);
    if (dev) {
        pci_dev_put(dev);
        return dev;
    }

    dev = pci_scan_device(bus, devfn);
    if (!dev)
        return NULL;

    pci_device_add(dev, bus);

    return dev;
}

/*
 * Read the config data for a PCI device, sanity-check it
 * and fill in the dev structure...
 */
static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
{
    struct pci_dev *dev;
    u32 l;

    if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
        return NULL;

    dev = pci_alloc_dev(bus);
    if (!dev)
        return NULL;

    dev->devfn = devfn;
    dev->vendor = l & 0xffff;
    dev->device = (l >> 16) & 0xffff;

    pci_set_of_node(dev);

    if (pci_setup_device(dev)) {
        pci_bus_put(dev->bus);
        kfree(dev);
        return NULL;
    }

    return dev;
}

bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
                int timeout)
{
    if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
        return false;

    /* some broken boards return 0 or ~0 if a slot is empty: */
    if (*l == 0xffffffff || *l == 0x00000000 ||
        *l == 0x0000ffff || *l == 0xffff0000)
        return false;

    if (pci_bus_crs_vendor_id(*l))
        return pci_bus_wait_crs(bus, devfn, l, timeout);

    return true;
}

#define PCI_OP_READ(size, type, len) \
int pci_bus_read_config_##size \
    (struct pci_bus *bus, unsigned int devfn, int pos, type *value)    \
{                                    \
    int res;                            \
    unsigned long flags;                        \
    u32 data = 0;                            \
    if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;    \
    pci_lock_config(flags);                        \
    res = bus->ops->read(bus, devfn, pos, len, &data);        \
    *value = (type)data;                        \
    pci_unlock_config(flags);                    \
    return res;                            \
}

static struct pci_ops pcie_ops_v2 = {
    .read  = pcie_config_read,
    .write = pcie_config_write,
};

/**
 * pci_setup_device - fill in class and map information of a device
 * @dev: the device structure to fill
 *
 * Initialize the device structure with information about the device's
 * vendor,class,memory and IO-space addresses,IRQ lines etc.
 * Called at initialisation of the PCI subsystem and by CardBus services.
 * Returns 0 on success and negative if unknown type of device (not normal,
 * bridge or CardBus).
 */
int pci_setup_device(struct pci_dev *dev)
{
    u32 class;
    u16 cmd;
    u8 hdr_type;
    int pos = 0;
    struct pci_bus_region region;
    struct resource *res;

    if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
        return -EIO;

    dev->sysdata = dev->bus->sysdata;
    dev->dev.parent = dev->bus->bridge;
    dev->dev.bus = &pci_bus_type;
    dev->hdr_type = hdr_type & 0x7f;
    dev->multifunction = !!(hdr_type & 0x80);
    dev->error_state = pci_channel_io_normal;
    set_pcie_port_type(dev);

    pci_dev_assign_slot(dev);
    /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
       set this higher, assuming the system even supports it.  */
    dev->dma_mask = 0xffffffff;

    dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
             dev->bus->number, PCI_SLOT(dev->devfn),
             PCI_FUNC(dev->devfn));

    pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
    dev->revision = class & 0xff;
    dev->class = class >> 8;            /* upper 3 bytes */

    dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
           dev->vendor, dev->device, dev->hdr_type, dev->class);

    /* need to have dev->class ready */
    dev->cfg_size = pci_cfg_space_size(dev);

    /* need to have dev->cfg_size ready */
    set_pcie_thunderbolt(dev);

    /* "Unknown power state" */
    dev->current_state = PCI_UNKNOWN;

    /* Early fixups, before probing the BARs */
    pci_fixup_device(pci_fixup_early, dev);
    /* device class may be changed after fixup */
    class = dev->class >> 8;

    if (dev->non_compliant_bars) {
        pci_read_config_word(dev, PCI_COMMAND, &cmd);
        if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
            dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
            cmd &= ~PCI_COMMAND_IO;
            cmd &= ~PCI_COMMAND_MEMORY;
            pci_write_config_word(dev, PCI_COMMAND, cmd);
        }
    }

    dev->broken_intx_masking = pci_intx_mask_broken(dev);

    switch (dev->hdr_type) {            /* header type */
    case PCI_HEADER_TYPE_NORMAL:            /* standard header */
        if (class == PCI_CLASS_BRIDGE_PCI)
            goto bad;
        pci_read_irq(dev);
        pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
        pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
        pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);

        /*
         * Do the ugly legacy mode stuff here rather than broken chip
         * quirk code. Legacy mode ATA controllers have fixed
         * addresses. These are not always echoed in BAR0-3, and
         * BAR0-3 in a few cases contain junk!
         */
        if (class == PCI_CLASS_STORAGE_IDE) {
            u8 progif;
            pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
            if ((progif & 1) == 0) {
                region.start = 0x1F0;
                region.end = 0x1F7;
                res = &dev->resource[0];
                res->flags = LEGACY_IO_RESOURCE;
                pcibios_bus_to_resource(dev->bus, res, &region);
                dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
                     res);
                region.start = 0x3F6;
                region.end = 0x3F6;
                res = &dev->resource[1];
                res->flags = LEGACY_IO_RESOURCE;
                pcibios_bus_to_resource(dev->bus, res, &region);
                dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
                     res);
            }
            if ((progif & 4) == 0) {
                region.start = 0x170;
                region.end = 0x177;
                res = &dev->resource[2];
                res->flags = LEGACY_IO_RESOURCE;
                pcibios_bus_to_resource(dev->bus, res, &region);
                dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
                     res);
                region.start = 0x376;
                region.end = 0x376;
                res = &dev->resource[3];
                res->flags = LEGACY_IO_RESOURCE;
                pcibios_bus_to_resource(dev->bus, res, &region);
                dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
                     res);
            }
        }
        break;

    case PCI_HEADER_TYPE_BRIDGE:            /* bridge header */
        if (class != PCI_CLASS_BRIDGE_PCI)
            goto bad;
        /* The PCI-to-PCI bridge spec requires that subtractive
           decoding (i.e. transparent) bridge must have programming
           interface code of 0x01. */
        pci_read_irq(dev);
        dev->transparent = ((dev->class & 0xff) == 1);
        pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
        set_pcie_hotplug_bridge(dev);
        pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
        if (pos) {
            pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
            pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
        }
        break;

    case PCI_HEADER_TYPE_CARDBUS:            /* CardBus bridge header */
        if (class != PCI_CLASS_BRIDGE_CARDBUS)
            goto bad;
        pci_read_irq(dev);
        pci_read_bases(dev, 1, 0);
        pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
        pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
        break;

    default:                    /* unknown header */
        dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
            dev->hdr_type);
        return -EIO;

    bad:
        dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
            dev->class, dev->hdr_type);
        dev->class = PCI_CLASS_NOT_DEFINED << 8;
    }

    /* We found a fine healthy device, go go go... */
    return 0;
}

static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
{
    unsigned int pos, reg;

    if (dev->non_compliant_bars)
        return;

    for (pos = 0; pos < howmany; pos++) {
        struct resource *res = &dev->resource[pos];
        reg = PCI_BASE_ADDRESS_0 + (pos << 2);
        pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
    }

    if (rom) {
        struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
        dev->rom_base_reg = rom;
        res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
                IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
        __pci_read_base(dev, pci_bar_mem32, res, rom);
    }
}

/**
 * pci_read_base - read a PCI BAR
 * @dev: the PCI device
 * @type: type of the BAR
 * @res: resource buffer to be filled in
 * @pos: BAR position in the config space
 *
 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
 */
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
            struct resource *res, unsigned int pos)
{
    u32 l = 0, sz = 0, mask;
    u64 l64, sz64, mask64;
    u16 orig_cmd;
    struct pci_bus_region region, inverted_region;

    mask = type ? PCI_ROM_ADDRESS_MASK : ~0;

    /* No printks while decoding is disabled! */
    if (!dev->mmio_always_on) {
        pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
        if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
            pci_write_config_word(dev, PCI_COMMAND,
                orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
        }
    }

    res->name = pci_name(dev);

    pci_read_config_dword(dev, pos, &l);
    pci_write_config_dword(dev, pos, l | mask);
    pci_read_config_dword(dev, pos, &sz);
    pci_write_config_dword(dev, pos, l);

    /*
     * All bits set in sz means the device isn't working properly.
     * If the BAR isn't implemented, all bits must be 0.  If it's a
     * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
     * 1 must be clear.
     */
    if (sz == 0xffffffff)
        sz = 0;

    /*
     * I don't know how l can have all bits set.  Copied from old code.
     * Maybe it fixes a bug on some ancient platform.
     */
    if (l == 0xffffffff)
        l = 0;

    if (type == pci_bar_unknown) {
        res->flags = decode_bar(dev, l);
        res->flags |= IORESOURCE_SIZEALIGN;
        if (res->flags & IORESOURCE_IO) {
            l64 = l & PCI_BASE_ADDRESS_IO_MASK;
            sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
            mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
        } else {
            l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
            sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
            mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
        }
    } else {
        if (l & PCI_ROM_ADDRESS_ENABLE)
            res->flags |= IORESOURCE_ROM_ENABLE;
        l64 = l & PCI_ROM_ADDRESS_MASK;
        sz64 = sz & PCI_ROM_ADDRESS_MASK;
        mask64 = PCI_ROM_ADDRESS_MASK;
    }

    if (res->flags & IORESOURCE_MEM_64) {
        pci_read_config_dword(dev, pos + 4, &l);
        pci_write_config_dword(dev, pos + 4, ~0);
        pci_read_config_dword(dev, pos + 4, &sz);
        pci_write_config_dword(dev, pos + 4, l);

        l64 |= ((u64)l << 32);
        sz64 |= ((u64)sz << 32);
        mask64 |= ((u64)~0 << 32);
    }

    if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
        pci_write_config_word(dev, PCI_COMMAND, orig_cmd);

    if (!sz64)
        goto fail;

    sz64 = pci_size(l64, sz64, mask64);
    if (!sz64) {
        dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
             pos);
        goto fail;
    }

    if (res->flags & IORESOURCE_MEM_64) {
        if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
            && sz64 > 0x100000000ULL) {
            res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
            res->start = 0;
            res->end = 0;
            dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
                pos, (unsigned long long)sz64);
            goto out;
        }

        if ((sizeof(pci_bus_addr_t) < 8) && l) {
            /* Above 32-bit boundary; try to reallocate */
            res->flags |= IORESOURCE_UNSET;
            res->start = 0;
            res->end = sz64;
            dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
                 pos, (unsigned long long)l64);
            goto out;
        }
    }

    region.start = l64;
    region.end = l64 + sz64;

    pcibios_bus_to_resource(dev->bus, res, &region);
    pcibios_resource_to_bus(dev->bus, &inverted_region, res);

    /*
     * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
     * the corresponding resource address (the physical address used by
     * the CPU.  Converting that resource address back to a bus address
     * should yield the original BAR value:
     *
     *     resource_to_bus(bus_to_resource(A)) == A
     *
     * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
     * be claimed by the device.
     */
    if (inverted_region.start != region.start) {
        res->flags |= IORESOURCE_UNSET;
        res->start = 0;
        res->end = region.end - region.start;
        dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
             pos, (unsigned long long)region.start);
    }

    goto out;

fail:
    res->flags = 0;
out:
    if (res->flags)
        dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);

    return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
}

void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
                 struct pci_bus_region *region)
{
    struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
    struct resource_entry *window;
    resource_size_t offset = 0;

    resource_list_for_each_entry(window, &bridge->windows) {
        struct pci_bus_region bus_region;

        if (resource_type(res) != resource_type(window->res))
            continue;

        bus_region.start = window->res->start - window->offset;
        bus_region.end = window->res->end - window->offset;

        if (region_contains(&bus_region, region)) {
            offset = window->offset;
            break;
        }
    }

    res->start = region->start + offset;
    res->end = region->end + offset;
}