ADS42LB69+ZYNQ zcu102调试记录

近期采用ZYNQ开发板zcu102，结合FMC的AD板卡做数据采集，AD采样频率250MHz，AD芯片是ADS42LB69，是一个双通道的高速AD，今天终于调通了一路，记录于此

首先最最重要的是时钟线的引脚分配，我之前就是被这个问题折磨的不行

set_property PACKAGE_PIN N9 [get_ports adc_1_dclk_p_in]    #ad的输出时钟，差分时钟250MHz
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_1_dclk_n_in]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_1_dclk_p_in]

set_property PACKAGE_PIN AG13 [get_ports rst_p]
set_property IOSTANDARD LVCMOS33 [get_ports rst_p]

set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets adc_1_clk_bufg_out]

set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property PACKAGE_PIN AG14 [get_ports led]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_ibufgds_adc_1/O]



set_property PACKAGE_PIN L13 [get_ports {adc_1_data_a_p_in[0]}]
set_property IOSTANDARD LVDS [get_ports {adc_1_data_a_p_in[0]}]
set_property PACKAGE_PIN L12 [get_ports {adc_1_data_a_p_in[1]}]
set_property IOSTANDARD LVDS [get_ports {adc_1_data_a_p_in[1]}]
set_property PACKAGE_PIN P12 [get_ports {adc_1_data_a_p_in[2]}]
set_property PACKAGE_PIN Y10 [get_ports {adc_1_data_a_p_in[3]}]
set_property PACKAGE_PIN T7 [get_ports {adc_1_data_a_p_in[4]}]
set_property IOSTANDARD LVDS [get_ports {adc_1_data_a_p_in[4]}]
set_property IOSTANDARD LVDS [get_ports {adc_1_data_a_p_in[3]}]
set_property IOSTANDARD LVDS [get_ports {adc_1_data_a_p_in[2]}]
set_property PACKAGE_PIN U9 [get_ports {adc_1_data_a_p_in[5]}]
set_property IOSTANDARD LVDS [get_ports {adc_1_data_a_p_in[5]}]
set_property PACKAGE_PIN Y12 [get_ports {adc_1_data_a_p_in[6]}]
set_property IOSTANDARD LVDS [get_ports {adc_1_data_a_p_in[6]}]
set_property PACKAGE_PIN Y4 [get_ports {adc_1_data_a_p_in[7]}]
set_property IOSTANDARD LVDS [get_ports {adc_1_data_a_p_in[7]}]

其中我的时钟的电平选择是：IOSTANDARD DIFF_HSTL_I_18

下面是顶层文件

//2021.10.09  HIT ATCI 
//采用ad4的输出时钟作为系统时钟，寄存器每一个上升沿记一次数，满1s后led的电平反转一次，并且采用ILA进行观测ad采集的16位数据，实验已通过
/*******************************************************************************/
module m_fmc_top(
input                       rst_p,
input						adc_1_dclk_p_in,
input						adc_1_dclk_n_in,
input			[ 7:0]	    adc_1_data_a_p_in,
input			[ 7:0]	    adc_1_data_a_n_in,
output                      led
); 
reg                        [28:0] cnt;
wire						adc_1_clk_bufg_out;
wire						adc_1_clk_bufg;  
wire	 		[15:0]	    adc_1_data_a_out;
assign led = (cnt<29'd250000000) ? 1'b0 : 1'b1;
always@(posedge adc_1_clk_bufg_out  or posedge rst_p)begin
    if(rst_p)
        cnt <= 29'd0;
    else if(cnt < 29'd500000000)
        cnt <=  cnt + 1'b1;
    else
        cnt <= 29'd0; 
end
IBUFGDS i_ibufgds_adc_1
(.I		(adc_1_dclk_p_in),
 .IB		(adc_1_dclk_n_in),
 .O		(adc_1_clk_bufg)
);
  adc_dcm  adc_dcm_inst
 (
  // Clock out ports
  .clk_out1(adc_1_clk_bufg_out),
  // Status and control signals
  .reset(0),
  .locked(),
 // Clock in ports
  .clk_in1(adc_1_clk_bufg)
 );  
 //例化一路AD
adc_iddr_interface adc_inst(
        .dclk_in(adc_1_clk_bufg_out),
        .rst_n(1'b1),
        .adc_data_p_in(adc_1_data_a_p_in),
        .adc_data_n_in(adc_1_data_a_n_in),
        .adc_data_out(adc_1_data_a_out)
);

ila_1 ilaadc_instance (
	.clk(adc_1_clk_bufg_out), // input wire clk


	.probe0(adc_1_data_a_out), // input wire [15:0]  probe0,ad输出结果
	.probe1(led) // input wire [0:0]  probe1  led灯
);
endmodule

adc_iddr_interface文件

`timescale 1ns/1ps
module adc_iddr_interface(//input
input						dclk_in,
input						rst_n,
input			[7:0]	adc_data_p_in,
input			[7:0]	adc_data_n_in,
//
output reg	[15:0]	adc_data_out
);
wire	[15:0]	adc_data;
wire	[15:0]	adc_demux0_data;
wire	[15:0]	adc_demux1_data;

always @(posedge dclk_in or negedge rst_n)
begin
	if(!rst_n)
		adc_data_out <= 16'b0;
	else
		begin
			adc_data_out[0]  <= adc_demux0_data[0];
			adc_data_out[1]  <= adc_demux1_data[0];
			adc_data_out[2]  <= adc_demux0_data[1];
			adc_data_out[3]  <= adc_demux1_data[1];
			adc_data_out[4]  <= adc_demux0_data[2];
			adc_data_out[5]  <= adc_demux1_data[2];
			adc_data_out[6]  <= adc_demux0_data[3];
			adc_data_out[7]  <= adc_demux1_data[3];
			adc_data_out[8]  <= adc_demux0_data[4];
			adc_data_out[9]  <= adc_demux1_data[4];
			adc_data_out[10] <= adc_demux0_data[5];
			adc_data_out[11] <= adc_demux1_data[5];
			adc_data_out[12] <= adc_demux0_data[6];
			adc_data_out[13] <= adc_demux1_data[6];
			adc_data_out[14] <= adc_demux0_data[7];
			adc_data_out[15] <= adc_demux1_data[7];
		end
end

parameter   SIZE = 4'd7;
genvar i;
generate 
begin
	for(i=0;i<=SIZE;i=i+1) 
	begin : ADC_DATA_IN
	
		IBUFDS #(
			.DIFF_TERM("TRUE"), // Differential Termination
			.IBUF_LOW_PWR("FALSE"), // Low power="TRUE", Highest performance="FALSE"
			.IOSTANDARD("DEFAULT") // Specify the input I/O standard
		)i_IBUFDS(
			.O(adc_data[i]), // Buffer output
			.I(adc_data_p_in[i]), // Diff_p buffer input (connect directly to top-level port)
			.IB(adc_data_n_in[i]) // Diff_n buffer input (connect directly to top-level port)
		);
	 

	 IDDRE1 #(
      .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), // IDDRE1 mode (OPPOSITE_EDGE, SAME_EDGE, SAME_EDGE_PIPELINED)
      .IS_CB_INVERTED(1'b0),          // Optional inversion for CB
      .IS_C_INVERTED(1'b0)            // Optional inversion for C
   )
   IDDRE1_inst (
      .Q1(adc_demux0_data[i]), // 1-bit output: Registered parallel output 1
      .Q2(adc_demux1_data[i]), // 1-bit output: Registered parallel output 2
      .C(dclk_in),   // 1-bit input: High-speed clock
      .CB(~dclk_in), // 1-bit input: Inversion of High-speed clock C
      .D(adc_data[i]),   // 1-bit input: Serial Data Input
      .R(0)    // 1-bit input: Active High Async Reset
   );
	end
end
endgenerate

endmodule

当我例化了集成逻辑分析仪ILA，并且生成bits stream下载的时候，却发现ILA的界面并没有正常打开，并且有以下报错：

WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xczu9 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ilaadc_instance' at location 'uuid_EFBFB818EFD05B079C45C67B1223FBDE' from probes file, since it cannot be found on the programmed device.

我们看其中的一句提示：

Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.

它告诉我们调试的时钟有问题，由于我使用的是AD输出的250MHz的高速时钟，并且经过了一个转接板，可能是时钟信号不够稳定，遇到这种问题，我们只需要在Vivado的左上角点击：

Refresh device