名称:四路计时器Verilog代码Quartus仿真(文末获取)
软件:Quartus
语言:Verilog
代码功能:
在quartus用Verilog,设计一个
四路计时器,
用四个按键输入控制计时器开始、暂停、复位,单按开始、暂停,长按复位,按键要有消抖电路,显示四个用6位数码管,四个按键分别控制四个数码管,计时范围是10us--10s
1. 工程文件
2. 程序文件
3. 程序编译
4. RTL图
4通道
单通道
5. Testbench
6. 仿真图
整体仿真图
分频模块
按键消抖模块
控制模块
显示模块
部分代码展示:
// Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM"Quartus II 64-Bit" // VERSION"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" // CREATED"Tue Apr 04 21:28:29 2023" module timmer_one( clk_in, key_in, bit_select, seg_select ); input wireclk_in; input wirekey_in; output wire[5:0] bit_select; output wire[7:0] seg_select; wireSYNTHESIZED_WIRE_0; wireSYNTHESIZED_WIRE_1; wire[7:0] SYNTHESIZED_WIRE_2; wire[7:0] SYNTHESIZED_WIRE_3; wire[7:0] SYNTHESIZED_WIRE_4; controlb2v_inst( .clk_100Hz(SYNTHESIZED_WIRE_0), .key_value(SYNTHESIZED_WIRE_1), .time_ms(SYNTHESIZED_WIRE_2), .time_s(SYNTHESIZED_WIRE_3), .time_us(SYNTHESIZED_WIRE_4)); displayb2v_inst1( .clk(clk_in), .time_ms(SYNTHESIZED_WIRE_2), .time_s(SYNTHESIZED_WIRE_3), .time_us(SYNTHESIZED_WIRE_4), .bit_select(bit_select), .seg_select(seg_select)); fenpingb2v_inst2( .clk_50M(clk_in), .clk_100Hz(SYNTHESIZED_WIRE_0)); key_jitterb2v_inst3( .clkin(clk_in), .key_in(key_in), .key_value(SYNTHESIZED_WIRE_1)); endmodule
源代码
扫描文章末尾的公众号二维码