参考链接:HDLBits导学
Problem 118 Simple FSM1 / Fsm1
问题:图中是一个有两个状态的摩尔型状态机。有一个输入信号与一个输出信号。本题中需要实现图中的状态机,注意复位后状态为 B,复位采用异步复位
思路:三段式状态机,详细解释参考上面链接
三段式分别指
- 状态跳转逻辑
- 状态触发器实现
- 输出逻辑
解决:
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state, next_state;
//状态跳转逻辑 根据输入信号以及当前状态确定状态的次态
always @(*) begin // This is a combinational always block
// State transition logic
case(state)
A:next_state = in ? A : B;
B:next_state = in ? B : A;
endcase
end
//状态触发器实现,在时钟边沿实现状态寄存器的跳变以及状态复位
always @(posedge clk, posedge areset) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if(areset)
state <= B;
else
state <= next_state;
end
//输出逻辑,根据当前状态实现输出
assign out = state;
// Output logic
// assign out = (state == ...);
endmodule
Problem 119 Simple FSM1 / Fsm2s
问题:此练习和上一个联系相同,但是采用同步复位的方式
解决:
// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
parameter A=0, B=1;
reg state, next_state;
//状态跳转逻辑 根据输入信号以及当前状态确定状态的次态
always @(*) begin // This is a combinational always block
// State transition logic
case(state)
A:next_state = in ? A : B;
B:next_state = in ? B : A;
endcase
end
//状态触发器实现,在时钟边沿实现状态寄存器的跳变以及状态复位
always @(posedge clk) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if(reset)
state <= B;
else
state <= next_state;
end
//输出逻辑,根据当前状态实现输出
assign out = state;
// Output logic
// assign out = (state == ...)
endmodule
(按照题目给的模板去写没有写出来,,,时序总是对不上)
Problem 120 Simple FSM2/ Fsm2
问题:这是一个具有两个状态、两个输入和一个输出的摩尔状态机。实现这个状态机
解决:
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
ON: next_state = k ? OFF : ON;
OFF: next_state = j ? ON : OFF;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)
state <= OFF;
else
state <= next_state;
end
// Output logic
// assign out = (state == ...);
assign out = state;
endmodule
Problem 121 Simple FSM2/ Fsm2s
问题:此练习和上一个练习一样,但是使用同步复位
解决:
module top_module(
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
ON: next_state = k ? OFF : ON;
OFF: next_state = j ? ON : OFF;
endcase
end
always @(posedge clk) begin
// State flip-flops with synchronous reset
if(reset)
state <= OFF;
else
state <= next_state;
end
// Output logic
// assign out = (state == ...);
assign out = state;
endmodule
Problem 122 Simple state transitions 3/ Fsm3comb
问题:下面是一个输入、一个输出、四个状态的摩尔状态机的状态转移表。使用以下状态编码:A=2'b00、B=2'b01、C=2'b10、D=2'b11。
仅为此状态机实现状态转换逻辑和输出逻辑(组合逻辑部分)。给定当前状态 ( state
),根据状态转换表计算next_state
和输出 ( out
)
解决:
module top_module(
input in,
input [1:0] state,
output [1:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: next_state = f(state, in)
always @(*) begin
case(state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: next_state = in ? D : A;
D: next_state = in ? B : C;
endcase
end
// Output logic: out = f(state) for a Moore state machine
assign out = (state==D);
endmodule
Problem 123 Simple one-hot state transitions 3/ Fsm3onehot
问题:下面是一个输入、一个输出、四个状态的摩尔状态机的状态转移表。使用以下状态编码:A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000。
通过检查假设编码来导出状态转换和输出逻辑方程。仅为此状态机实现状态转换逻辑和输出逻辑(组合逻辑部分)。(测试平台将使用非一个热输入进行测试,以确保您不会尝试做一些更复杂的事情)
解决:
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = (state[A] & ~in) || (state[C] & ~in);
assign next_state[B] = (state[B] & in) || (state[D] & in) || (state[A] & in);
assign next_state[C] = (state[B] & ~in) || (state[D] & ~in);
assign next_state[D] = (state[C] & in);
// Output logic:
assign out = state[D];
endmodule
注意:最后的输出是该状态位为1
Problem 124 Simple FSM3/ Fsm3
问题:下面是一个输入、一个输出、四个状态的摩尔状态机的状态转移表。实现这个状态机。异步复位到状态A
解决:
module top_module(
input clk,
input in,
input areset,
output out); //
parameter A=0, B=1, C=2, D=3;
reg[1:0] state,next_state;
// State transition logic
always @(*) begin
case(state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: next_state = in ? D : A;
D: next_state = in ? B : C;
endcase
end
// State flip-flops with asynchronous reset
always @(posedge clk or posedge areset) begin
if(areset)
state <= A;
else
state <= next_state;
end
// Output logic
assign out = (state == D);
endmodule
Problem 125 Simple FSM3/ Fsm3s
问题:此题和上一题一样,只是使用了同步复位
解决:
module top_module(
input clk,
input in,
input reset,
output out); //
parameter A=0, B=1, C=2, D=3;
reg[1:0] state,next_state;
// State transition logic
always @(*) begin
case(state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: next_state = in ? D : A;
D: next_state = in ? B : C;
endcase
end
// State flip-flops with asynchronous reset
always @(posedge clk) begin
if(reset)
state <= A;
else
state <= next_state;
end
// Output logic
assign out = (state == D);
endmodule
Problem 126 Design a Moore FSM/Exams/ece241 2013 q4
问题:大概意思就是:当水位达到最大值,也就是s1s2s3都输出高电平的时候,水流量为0,也就是f1f2f3和dfr都输出低电平,当水位低于最低值,也就是s1s2s3都输出低电平的时候,水流量要最大,也就是f1f2f3和dfr都输出高电平。然后就是水位在最高和最低之前的时候,f1f2f3的输出看表就好,什么状态哪一个要输出高电平。dfr则需要看上一次水位的改变是什么,如果上一次水位在减少,那就输出高电平,反之输出低电平。注意,此处指的是上一次水位的变化,而不是上一个时钟沿水位的状态
还包括一个高电平有效同步复位,该复位将状态机复位到相当于水位长时间处于低位的状态(没有传感器有效时,所有四个输出都为高电平)
解决:
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
//四个状态
//空闲状态 fr1输出状态 fr1和fr2输出状态 fr1,fr2,fr3都输出的状态
parameter Idle=0,Fr1O=1,Fr12O=2,Fr123O=3;
//状态保存 上一次状态 本次状态 下一次状态
reg[1:0] pre_state,state,next_state;
//不管什么状态都会发生的状态改变
always @(*) begin
case(s)
3'b000: next_state <= Fr123O;
3'b001: next_state <= Fr12O;
3'b011: next_state <= Fr1O;
3'b111: next_state <= Idle;
default: next_state <= state;
endcase
end
always @(posedge clk) begin
if(reset) begin
state <= Fr123O;
if(state != next_state)
pre_state <= state;
end
else begin
state <= next_state;
//保证上一次的状态和本次的状态不会是相同状态
//针对 7->3->3 或是 3->1->1->1都需要输出dfr
//不可能定义不定个上一次状态来保存各种上一次状态
//所以上一次状态就让它不同于本次状态
if(state != next_state)
pre_state <= state;
end
end
//输出
assign fr1 = (state == Fr1O||state == Fr12O||state == Fr123O);
assign fr2 = (state == Fr12O||state == Fr123O);
assign fr3 = (state == Fr123O);
//当三个都输出的时候 dfr也要输出,然后就是本次的水位比上一次的低
//当然指的是在本次状态发生改变的情况,没有发生改变还得看发生改变那一次的水位变化是怎样的
assign dfr = (pre_state < state) || (state == Fr123O);
endmodule
注意:这个题主要就是dfr的输出比较难搞