verilog实现“101”序列检测器

题目：序列检测器

有“101”序列输入时输出为1，其他输入情况下，输出为0。画出状态转移图，并用verilog描述。
画出状态图：

三段式状态机：

module sequence_detection (
	input clk,
	input rst_n,
	input data_in,
	
	output reg data_out,
	/***/
	output reg [2:0] now_state,
	output reg [2:0] next_state
	
	
);
//参数定义
parameter s0='d0,s1='d1,s2='d2,s3='d3;
/**
reg [2:0] now_state;
reg [2:0] next_state;
*/
//第一段，状态复位，次态赋值给当前状态
always @(posedge clk or negedge rst_n)begin
	if(rst_n==1'b0)
		now_state <= 1'b0;
	else
		now_state <= next_state;
end 

//状态的跳转
always @(posedge clk or negedge rst_n )begin
/**	case(now_state)
		s0:
			if()
	endcase 
	if()
***/
	case(next_state)
		s0:next_state <= data_in?s1:s0;
		s1:next_state <= data_in?s1:s2;
		s2:next_state <= data_in?s3:s0;
		s3:next_state <= data_in?s1:s2;
		default:next_state=s0;
	endcase

end 


//输出

/***********/
always @(posedge clk or negedge rst_n )begin
	if(rst_n == 1'b0)
		data_out <= 1'b0;
	else if(next_state == s3)
		data_out <= 'b1;
	else
		data_out <= 1'b0;
end 



endmodule 

module sequence_detection_tb ();
reg clk;
reg rst_n;
reg data_in;

wire data_out;
/****/
wire [2:0] next_state;
wire [2:0] now_state;

//4字符16位
reg [31:0]              state_name  ;
parameter s0=0,s1=1,s2=2,s3=3;





//变量初始化，赋值
initial begin
	clk = 'b0;
	rst_n ='b0;
	data_in = 'b0;
	
	#10
	clk = 'b1;
	rst_n ='b1;
	#10
	data_in='b1;
	#10
	data_in = 'b0;
	#10
	data_in = 'b1;
	#10
	data_in = 'b0;
	#10
	data_in = 'b1;
	#10
	data_in = 'b0;
	#10
	data_in = 'b0;
	#10
	data_in ='b1;
	#10
	data_in = 'b1;
	#10
	data_in='b1;
	#10
	data_in = 'b0;
	#10
	data_in = 'b1;
	#10
	data_in = 'b0;
	#10
	data_in = 'b1;
	#10
	data_in = 'b0;
	#10
	data_in = 'b0;
	#10
	data_in ='b1;
	#10
	data_in = 'b1;
	
	

end 

//时钟
always #5 clk=~clk;

//例化
sequence_detection u0(
	.clk		(clk		),
	.rst_n		(rst_n		),
	.data_in	(data_in	),
	
	.data_out	(data_out	),
	/*****/
	.now_state	(now_state	),
	.next_state	(next_state	)
	
);
//在波形中显示对应的状态名称
always@(*)begin
    case(u0.now_state)//u0为例化模块的名称，now_state为u0的内部信号。在modelsim中改为ASCII,就可以显示字符串了
        s0:       state_name = "s0";
        s1:       state_name = "s1";
        s2:       state_name = "s2";
        s3:       state_name = "s3";
        default:  state_name = "s0";
    endcase
end

endmodule 

实验结果：

注意：

今天在ModelSim中遇到一个bug:

# No Design Loaded!

之前也遇到过这样的问题，我大概知道原因：

1、仿真文件中的模块例化中端口和模块的端口不对应
2、例化中多一个逗号，或者少一个逗号
3、例化时模块名称后没有给它重新命名

我反复检查代码发现也没有发现错误呀，给我郁闷了好久。后面把ModelSim关闭重启就可以加载了，这个bug就被解决了 ，居然那么简单。

	--晓凡	2023年6月11日于桂林书