一、仿真概述
1、实际仿真时,需要一个仿真器(modelsim)。仿真时通常需要两个输入,设计描述和驱动设计的激励文件。
2、仿真模型:
3、仿真流程图:
二、TestBench文件的编写
1、测试文件的基本机构
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY test_bench IS --测试文件的实体,一般为空
END test_bench;
ARCHITECTURE tb_behav OF test_bench IS
COMPONENT name_entity_test --被测元件声明
PORT(
input_name : IN STD_LOGIC;
bidir_name : IN STD_LOGIC;
output_name :OUT STD_LOGIC );
END COMPONENT;
--locial_signal_declaration --局部信号声明
BEGIN
instance_name : name_entity_test --被测元件例化
PORT MAP
(
component_port => connect_name
);
L1: PROCESS () --进程L1,产生时钟信号
--....
END PROCESS;
L2: PROCESS () --进程L2,产生时激励信号
--....
END PROCESS;
END tb_behav;
2、一个简单设计文件以及测试文件的例子
设计文件:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY counter IS
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END counter;
ARCHITECTURE bev OF counter IS
SIGNAL temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk,reset)
BEGIN
IF (reset = '1') THEN
temp <= "0000";
ELSIF (clk'EVENT AND clk = '1')THEN
temp <= temp +1;
END IF;
END PROCESS;
count <= temp;
END bev;
测试文件
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY tb_counter IS --定义空实体
END tb_counter;
ARCHITECTURE tb_bev OF tb_counter IS
COMPONENT counter --元件声明
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk : STD_LOGIC := '0'; --信号定义
SIGNAL reset : STD_LOGIC := '0';
SIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT clk_period := 20 NS;
BEGIN
U1 : counter PORT MAP --元件例化
(clk => clk;
reset => reset;
count => count);
clk_gen:PROCESS
BEGIN
clk <= '1';
WAIT FOR clk_period/2;
clk <= '0';
WAIT FOR clk_period/2;
END PROCESS;
tb: PROCESS
BEGIN
WAIT FOR 20 NS;
reset <= '1';
WAIT FOR 20 NS;
reset <= '0';
WAIT FOR 200 NS;
WAIT;
END PROCESS
END tb_bev;