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题目一(MUX)
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output out );
assign out = (~sel & a) | (sel & b);
endmodule
我的修正(一)
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0]out );
assign out = sel?a:b;
endmodule
题目二(NAND)
This three-input NAND gate doesn't work. Fix the bug(s).
You must use the provided 5-input AND gate:
module andgate ( output out, input a, input b, input c, input d, input e );
module top_module (input a, input b, input c, output out);//
andgate inst1 ( a, b, c, out );
endmodule
我的修正(二)
module top_module (input a, input b, input c, output out);//
wire out1;
andgate inst1 ( out1, a, b, c,1,1 )