Verilog练习：HDLBits笔记17

最新推荐文章于 2024-04-28 22:18:44 发布

WinstonQQM

最新推荐文章于 2024-04-28 22:18:44 发布

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本文链接：https://blog.csdn.net/WinstonQQM/article/details/121626716

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本文探讨了五个编程挑战：8位MUX、3输入NAND门、4-to-1 MUX、加减运算器与零标志、8位键盘代码识别。每个问题都提供了源代码错误分析，并给出了修正后的解决方案。通过实践理解与调试技巧，提升代码正确性。

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五、Reading Simulations

Finding bugs in codes

1、MUX

Problem Statement：

This 8-bit wide 2-to-1 multiplexer doesn't work. Fix the bug(s).

//Source Code
module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output out  );

    assign out = (~sel & a) | (sel & b);

endmodule

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output[7:0]out  );

    assign out = sel ? a : b;

endmodule

2、NAND

Problem Statement：

This three-input NAND gate doesn't work. Fix the bug(s).

You must use the provided 5-input AND gate:
module andgate ( output out, input a, input b, input c, input d, input e );

//Source Code
module top_module (input a, input b, input c, output out);//

    andgate inst1 ( a, b, c, out );

endmodule

module top_module (input a, input b, input c, output out);
    
    wire out1;
    
    assign out = ~out1;

    andgate instance1 (.out(out1), .a(a), .b(b), .c(c), .d(1'b1), .e(1'b1),);

endmodule

3、MUX

Problem Statement：

This 4-to-1 multiplexer doesn't work. Fix the bug(s).

You are provided with a bug-free 2-to-1 multiplexer:
module mux2 (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out
);

//Source Code
module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire mux0, mux1;
    mux2 mux0 ( sel[0],    a,    b, mux0 );
    mux2 mux1 ( sel[1],    c,    d, mux1 );
    mux2 mux2 ( sel[1], mux0, mux1,  out );

endmodule

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); 

    wire [7:0]mux0;
    wire [7:0]mux1;
    
    mux2 instance1(.sel(sel[0]), .a(a), .b(b), .out(mux0));
    mux2 instance2(.sel(sel[0]), .a(c), .b(d), .out(mux1));
    mux2 instance3(.sel(sel[1]), .a(mux0), .b(mux1), .out(out));    
	   
endmodule

4、Add/sub

Problem Statement：

The following adder-subtractor with zero flag doesn't work. Fix the bug(s).

//Source Code
// synthesis verilog_input_version verilog_2001
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase

        if (~out)
            result_is_zero = 1;
    end

endmodule

module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output[7:0] out,
    output result_is_zero
);

    always @(*) begin
        	case (do_sub)
          	0: out = a+b;
          	1: out = a-b;
        	endcase
    end
    
    assign result_is_zero = (out == 0) ? 1 : 0;

endmodule

5、Case statement

Problem Statement：

This combinational circuit is supposed to recognize 8-bit keyboard scancodes for keys 0 through 9. It should indicate whether one of the 10 cases were recognized (valid), and if so, which key was detected. Fix the bug(s).

//Source Code
module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid=1 );//

     always @(*)
        case (code)
            8'h45: out = 0;
            8'h16: out = 1;
            8'h1e: out = 2;
            8'd26: out = 3;
            8'h25: out = 4;
            8'h2e: out = 5;
            8'h36: out = 6;
            8'h3d: out = 7;
            8'h3e: out = 8;
            6'h46: out = 9;
            default: valid = 0;
        endcase

endmodule

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid=1 );//

     always @(*)
        case (code)
            8'h45: begin
                out = 0;
                valid = 1;
            end
            8'h16: begin
                out = 1;
                valid = 1;
            end
            8'h1e: begin
                out = 2;
                valid = 1;
            end
            8'h26: begin
                out = 3;
                valid = 1;
            end
            8'h25: begin
                out = 4;
                valid=1;
            end
            8'h2e: begin
                out = 5;
                valid = 1;
            end
            8'h36: begin
                out = 6;
                valid = 1;
            end
            8'h3d: begin
                out = 7;
                valid = 1;
            end
            8'h3e: begin
                out = 8;
                valid = 1;
            end
            8'h46: begin
                out = 9;
                valid = 1;
            end
            default: begin
                out = 0;
                valid = 0;
            end
        endcase

endmodule