ODDR2的使用

1.SPartan6 FPGA中， PLL产生的时钟不能直接连到FPGA的通用I/O上；

2.如果硬件已经连上了，可通过在PLL输出与通用I/O之间增加ODDR2模块缓冲来解决。

3.ODDR2与PLL模块可放在一个V文件中。

4.ODDR2模块如下：

  ODDR2 #(
    .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
    .INIT(1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1
    .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
    ) U_ODDR2_PLL输出时钟名 (
      .Q(oddr2_I/O管脚名),   // 1-bit DDR output data
      .C0(clock_PLL输出时钟名),   // 1-bit clock input
      .C1(~clock_PLL输出时钟名),   // 1-bit clock input
      .CE(1'b1), // 1-bit clock enable input
      .D0(1'b1), // 1-bit data input (associated with C0)
      .D1(1'b0), // 1-bit data input (associated with C1)
      .R(1'b0),   // 1-bit reset input
      .S(1'b0)    // 1-bit set input
    );

只用OBUFDS是不行的，编译报错，错误内容如下
/
ERROR:Place:1205 - This design contains a global buffer instance,
   <OUT20_40M/clkout2_buf>, driving the net, <CLK_OUT40M>, that is driving the
   following (first 30) non-clock load pins off chip.
   < PIN: MyPrimitive/ADCLK400M_P.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_EditERROR
/
上面大致内容是：时钟驱动片外非时钟端口，在Spartan-6中会导致全局网络布线受限，即使布线
后，会导致过大的延迟和抖动，两种改进方法：1.在OBUFDS前使用ODDR2。 2.在UCF中使用专
用约束语句， < PIN "OUT20_40M/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
忽略错误，但会给出警告。