github上包含SystemVerilog的仓库

NAME	OWNER	STARS	URL	DESCRIPTION
hdmi	hdl-util	472	https://github.com/hdl-util/hdmi	Send video/audio over HDMI on an FPGA
nontrivial-mips	trivialmips	394	https://github.com/trivialmips/nontrivial-mips	NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
axi	pulp-platform	198	https://github.com/pulp-platform/axi	AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilogReference	VerificationExcellence	188	https://github.com/VerificationExcellence/SystemVerilogReference	training labs and examples
logic	tymonx	136	https://github.com/tymonx/logic	CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog-mode	veripool	113	https://github.com/veripool/verilog-mode	Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
sv-tests	SymbiFlow	92	https://github.com/SymbiFlow/sv-tests	Test suite designed to check compliance with the SystemVerilog standard.
common_cells	pulp-platform	73	https://github.com/pulp-platform/common_cells	Common SystemVerilog components
fx68k	ijor	71	https://github.com/ijor/fx68k	FX68K 68000 cycle accurate SystemVerilog core
USTC-RVSoC	WangXuan95	66	https://github.com/WangXuan95/USTC-RVSoC	FPGA-based RISC-V CPU+SoC.
TrivialMIPS	trivialmips	61	https://github.com/trivialmips/TrivialMIPS	MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
Deep-Neural-Network-Hardware-Accelerator	StefanSredojevic	52	https://github.com/StefanSredojevic/Deep-Neural-Network-Hardware-Accelerator	SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software
svaunit	amiq-consulting	49	https://github.com/amiq-consulting/svaunit	SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
SystemVerilogAssertions	VerificationExcellence	47	https://github.com/VerificationExcellence/SystemVerilogAssertions	Examples and reference for System Verilog Assertions
tvip-axi	taichi-ishitani	47	https://github.com/taichi-ishitani/tvip-axi	AMBA AXI VIP
systemverilog.io	subbdue	46	https://github.com/subbdue/systemverilog.io	Code used in
AHB2	GodelMachine	43	https://github.com/GodelMachine/AHB2	AMBA AHB 2.0 VIP in SystemVerilog UVM
SystemVerilogSHA256	unixb0y	37	https://github.com/unixb0y/SystemVerilogSHA256	SHA256 in (System-) Verilog / Open Source FPGA Miner
tnoc	taichi-ishitani	37	https://github.com/taichi-ishitani/tnoc	Network on Chip Implementation written in SytemVerilog
FPGA-Application-Development-and-Simulation	loykylewong	36	https://github.com/loykylewong/FPGA-Application-Development-and-Simulation	《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
gateware	swetland	33	https://github.com/swetland/gateware	A collection of little open source FPGA hobby projects
FTDI-245fifo-interface	WangXuan95	32	https://github.com/WangXuan95/FTDI-245fifo-interface	FPGA-based USB fast communication using FT232H/FT600 chip.
riscv-vip	jerralph	29	https://github.com/jerralph/riscv-vip	For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
fpga-virtual-console	Harry-Chen	29	https://github.com/Harry-Chen/fpga-virtual-console	VT220-compatible console on Cyclone IV EP4CE55F23I7
FM_Radio	pbing	28	https://github.com/pbing/FM_Radio	Simple mono FM Radio.
combinator-uvm	doswellf	27	https://github.com/doswellf/combinator-uvm	UVM Testbench For SystemVerilog Combinator Implementation
amiq_apb	amiq-consulting	26	https://github.com/amiq-consulting/amiq_apb	SystemVerilog VIP for AMBA APB protocol
aes128-hdl	mbgh	25	https://github.com/mbgh/aes128-hdl	A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.
virtio	tymonx	23	https://github.com/tymonx/virtio	Virtio implementation in SystemVerilog
AES	cjdrake	22	https://github.com/cjdrake/AES	Advanced Encryption Standard (AES) SystemVerilog Core
fpga-hash-table	johan92	21	https://github.com/johan92/fpga-hash-table	Simple hash table on Verilog (SystemVerilog)
systemverilog-design-patterns	tenthousandfailures	21	https://github.com/tenthousandfailures/systemverilog-design-patterns	None
NoCRouter	agalimberti	20	https://github.com/agalimberti/NoCRouter	RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
custom_uvm_report_server	kaushalmodi	18	https://github.com/kaushalmodi/custom_uvm_report_server	Customized UVM Report Server
verilog-sid-mos6581	thomask77	17	https://github.com/thomask77/verilog-sid-mos6581	MOS6581 SID chip emulator in SystemVerilog
sv-1800-2012	gvekony	17	https://github.com/gvekony/sv-1800-2012	IEEE Std 1800™-2012: IEEE Standard for SystemVerilog – Unified Hardware Design, Specification, and Verification Language syntax definition for VS Code
svx	mxg	16	https://github.com/mxg/svx	SystemVerilog Extension Library – a library of utilities for generic programming and increased productivity
verilog-format	jiegec	16	https://github.com/jiegec/verilog-format	A naive verilog/systemverilog formatter
system-verilog-patterns	luuvish	15	https://github.com/luuvish/system-verilog-patterns	SystemVerilog Design Patterns
sv_image	nelsoncsc	15	https://github.com/nelsoncsc/sv_image	Reusable image processing modules in SystemVerilog
CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2	karthisugumar	15	https://github.com/karthisugumar/CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2	A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator
nanoFOX	Dmitriy0111	14	https://github.com/Dmitriy0111/nanoFOX	A small RISC-V core (SystemVerilog)
FPGA-SDcard-Reader	WangXuan95	14	https://github.com/WangXuan95/FPGA-SDcard-Reader	FPGA-based SDcard Reader via SD bus.
uvm_debug	uvmdebug	13	https://github.com/uvmdebug/uvm_debug	UVM interactive debug library
jtag_dpi	pulp-platform	12	https://github.com/pulp-platform/jtag_dpi	JTAG DPI module for SystemVerilog RTL simulations
sms	celesteneary	12	https://github.com/celesteneary/sms	Sega Master System in SystemVerilog
nim-systemverilog-dpic	kaushalmodi	11	https://github.com/kaushalmodi/nim-systemverilog-dpic	Using Nim to interface with SystemVerilog test benches via DPI-C
svreal	sgherbst	11	https://github.com/sgherbst/svreal	Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
axi_node	pulp-platform	10	https://github.com/pulp-platform/axi_node	AXI X-Bar
Cryptography-in-Systemverilog	zhouchuanrui	10	https://github.com/zhouchuanrui/Cryptography-in-Systemverilog	A collection of cryptographic algorthms implemented in SystemVerilog
axi4-interface	mmxsrup	10	https://github.com/mmxsrup/axi4-interface	AXI4 and AXI4-Lite interface definitions
SHIT-Core-NSCSCC2020	Superscalar-HIT-Core	10	https://github.com/Superscalar-HIT-Core/SHIT-Core-NSCSCC2020	a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
ahb3lite_pkg	RoaLogic	9	https://github.com/RoaLogic/ahb3lite_pkg	Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
sv_csv_parser	Mochenx	9	https://github.com/Mochenx/sv_csv_parser	A CSV file parser, written in SystemVerilog
jarvisuk	shady831213	9	https://github.com/shady831213/jarvisuk	Just A Really Very Impressive Systemverilog UVM Kit
freecellera-uvm	Freecellera	8	https://github.com/Freecellera/freecellera-uvm	Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)
Verilog-FixedPoint	WangXuan95	8	https://github.com/WangXuan95/Verilog-FixedPoint	Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version.
common_verification	pulp-platform	7	https://github.com/pulp-platform/common_verification	SystemVerilog modules and classes commonly used for verification
reflection	tudortimi	7	https://github.com/tudortimi/reflection	Reflection API for SystemVerilog
vpi	tudortimi	7	https://github.com/tudortimi/vpi	SystemVerilog wrapper over the Verilog Programming Interface (VPI)
YasaUvk	zhajio1988	7	https://github.com/zhajio1988/YasaUvk	🐛UVM verification kits which uses YASA as simulation script
dragonphy2	StanfordVLSI	7	https://github.com/StanfordVLSI/dragonphy2	Open Source PHY v2
NN_Network_On_Chip	eanchlia	7	https://github.com/eanchlia/NN_Network_On_Chip	Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to interface four instances of neural engine with AHB bus to create NOC.
constraintlayering	tenthousandfailures	6	https://github.com/tenthousandfailures/constraintlayering	SystemVerilog Constraint Layering via Reusable Randomization Policy Classes Examples
tbcm	taichi-ishitani	6	https://github.com/taichi-ishitani/tbcm	Basic Common Modules
FPGA-SDcard-Reader-SPI	WangXuan95	6	https://github.com/WangXuan95/FPGA-SDcard-Reader-SPI	FPGA-based SDcard Reader via SPI.
SystemVerilog	yuxuanZh	5	https://github.com/yuxuanZh/SystemVerilog	This is a code repo for previous projects in Digital Design & Verification
AHB-SystemVerilog	forever-gk	5	https://github.com/forever-gk/AHB-SystemVerilog	None
yamm	amiq-consulting	5	https://github.com/amiq-consulting/yamm	YAMM package repository
Gaia	GeraltShi	5	https://github.com/GeraltShi/Gaia	Generate UVM testbench framework template files with Python 3
SV-for-Design	jomonkjoy	5	https://github.com/jomonkjoy/SV-for-Design	Systemverilog Design Packages
usb20dev	esynr3z	5	https://github.com/esynr3z/usb20dev	USB 2.0 FS Device controller IP core written in SystemVerilog
gpio_agent	imokanj	5	https://github.com/imokanj/gpio_agent	General Purpose I/O agent written in UVM
Fake-SDcard	WangXuan95	5	https://github.com/WangXuan95/Fake-SDcard	Imitate SDcard using FPGAs.
LLAPI	Kitrinx	5	https://github.com/Kitrinx/LLAPI	Bliss-Box Low Latency API Implementation in SystemVerilog
entc_missing_semester	abarajithan11	5	https://github.com/abarajithan11/entc_missing_semester	An initiative to familiarize the students of ENTC with tools (Vivado…) and languages (SystemVerilog…)
aes128	smartfoxdata	5	https://github.com/smartfoxdata/aes128	The aes128 is a SystemVerilog implementation of the AES algorithm with 128-bit key
SonyCellSPU	ppujari24	5	https://github.com/ppujari24/SonyCellSPU	Implementation of a Dual Issue Pipelined Multimedia Processor Architecture (SONY Cell SPU) in SystemVerilog
sva_traces	go2uvm	5	https://github.com/go2uvm/sva_traces	Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors
SystemVerilog_TB	scott7950	4	https://github.com/scott7950/SystemVerilog_TB	SystemVerilog Testbench
System-Snake	andrewandrepowell	4	https://github.com/andrewandrepowell/System-Snake	Snake game implemented in SystemVerilog, running on the Digilent Nexys DDR 4.
Single-Cycle-Processor	tianrenz2	4	https://github.com/tianrenz2/Single-Cycle-Processor	Single-Cycle RISC-V Processor in systemverylog
Digital-piano-in-SystemVerilog	z-e-r-0	4	https://github.com/z-e-r-0/Digital-piano-in-SystemVerilog	This project is compatible for BASYS3 and Beti Board. It has 4 modules (incuding top module).
HDL-Safe	arokasprz100	4	https://github.com/arokasprz100/HDL-Safe	Simple safe lock mechanism written in SystemVerilog.
crc_calc	hellgate202	4	https://github.com/hellgate202/crc_calc	Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
riscv_asm_sv	jeras	4	https://github.com/jeras/riscv_asm_sv	RISC-V assembler/dis-assembler written in SystemVerilog
svlint-action	dalance	4	https://github.com/dalance/svlint-action	None
tue	taichi-ishitani	4	https://github.com/taichi-ishitani/tue	Useful UVM extensions
uvmgen	edcote	4	https://github.com/edcote/uvmgen	UVM verification component and testbench generator tool
fpga-projects	alisemi	4	https://github.com/alisemi/fpga-projects	FPGA Projects written using SystemVerilog, Verilog, and VHDL are put here in seperate folders.
cagt	amiq-consulting	4	https://github.com/amiq-consulting/cagt	Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast an UVM based agent for any protocol.
tvip-apb	taichi-ishitani	4	https://github.com/taichi-ishitani/tvip-apb	Verification IP for AMBA APB Protocol
Hard-JPEG-LS	WangXuan95	4	https://github.com/WangXuan95/Hard-JPEG-LS	FPGA-based JPEG-LS image encoder in near-lossless mode.
systemverilog	zstechly	3	https://github.com/zstechly/systemverilog	System Verilog Presentation / example code I wrote to use as a template for future test benches
Memory	chenyangbing	3	https://github.com/chenyangbing/Memory	None
FPGA-Fighting-Game	seanluo1	3	https://github.com/seanluo1/FPGA-Fighting-Game	I created a two-player fighting game that can be played on an Altera Cyclone IV FPGA.
Async_FIFO_Verification	akzare	3	https://github.com/akzare/Async_FIFO_Verification	Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
sv_practice	harpreetbhatia	3	https://github.com/harpreetbhatia/sv_practice	Practice exercises for SystemVerilog, UVM …
digital_circuits	anthonyabeo	3	https://github.com/anthonyabeo/digital_circuits	A collection of digital logic circuits
HDL	embeddedmoscow	3	https://github.com/embeddedmoscow/HDL	Verilog & SystemVerilog examples for articles