遇到一个小问题：用到两个MMCM是会冲突，抢输入时钟引脚，会相互排它，无解

问题描述：工程中要用到两个clk_wiz，按道理说这两个mmcm（时钟模块）的输入都是CLK_100M，即两个模块的输入是同一个信号，（实际上芯片也只有一个时钟管脚），但是implement失败，

有两个critical warning：

1、[Shape Builder 18-119] Failed to create I/OLOGIC Route Through shape for instance u_clk_1/inst/clkin1_ibufg. Found overlapping instances within the shape: u_clk_0/inst/clkin1_ibufg and u_clk_1/inst/clkin1_ibufg.

2、[Vivado 12-1411] Cannot set LOC property of ports, Instance u_clk_1/inst/clkin1_ibufg can not be placed in INBUF_EN of site IOB_X0Y74 because the bel is occupied by u_clk_0/inst/clkin1_ibufg. This could be caused by bel constraint conflict ["E:/fpga/xilinx/Vivado/HDMI/HDMI_coe/hdmi_display_demon/hdmi_display_demon.srcs/constrs_1/new/zynq_pin.xdc":7]

有一个error：

1、[DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 14 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: clk_100M.

其实用一个MMCM也是可以的，只不过想重新生成一个比较准确的时钟，所以想再写一个PLL，片子有两个MMCM和两个PLL。

试了以下方法：

1，将MMCM改成PLL；好像也不行

error：

ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 14 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: clk_100M.

大概是LOC（特定位置约束）有冲突

2，新建工程，专门测试两个MMCM共存的情况；

 

 

最后的解决办法：时钟嵌套。

20200604补充：

ug472，72页：

The CLKOUT0–CLKOUT3 of either the MMCM or PLL can be used to cascade to other MMCMs/PLLs. However, there is a phase offset on the output clocks between cascaded MMCMs/PLLs.

73页：

Cascading MMCMs/PLLs can only occur with adjacent CMTs。